----------------------------------------------------------------------------
--  top.vhd
--	Top for XSIM Example
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;


entity top is
    port (
	clk : in std_logic;
	data : out std_logic
    );
end entity;


architecture RTL of top is
    signal count : unsigned(3 downto 0) := "0000";
begin

    sub_inst : entity work.sub
	port map (
	    A => count(3),
	    B => count(2),
	    C => clk,
	    Q => data);

    count_proc : process(clk)
    begin
	if rising_edge(clk) then
	    count <= count + "1";
	end if;
    end process;

end RTL;