----------------------------------------------------------------------------
--  sub.vhd
--	Submodule for XSIM Example
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;


entity sub is
    port (
	A : in std_logic;
	B : in std_logic;
	C : in std_logic;
	Q : out std_logic
    );
end entity;

architecture RTL of sub is
    signal comb : std_logic;
begin

    comb <= A xor B;

    clk_proc : process(C)
        variable cnt_v : natural range 0 to 7 := 0;
    begin
	if rising_edge(C) then
	    if cnt_v = 7 then
		cnt_v := 0;
		Q <= comb;
	    else
		cnt_v := cnt_v + 1;
	    end if;
	end if;
    end process;

end RTL;