----------------------------------------------------------------------------
--  chain.vhd
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;

library UNISIM;
use UNISIM.vcomponents.ALL;

entity chain is
    port (a : in std_logic; b : out std_logic);
end entity;

architecture RTL of chain is

    constant LENGTH : natural := 10400*4;

    signal vector : std_logic_vector(LENGTH downto 0);

begin
    CHAIN : for I in 0 to LENGTH-1 generate
	LUT1_inst : LUT1
	    generic map (INIT => "01")
	    port map (
		I0 => vector(I),
		O => vector(I+1) );
    end generate;

    vector(0) <= a;
    b <= vector(LENGTH);

end RTL;