----------------------------------------------------------------------------
--  top.vhd
--	Simple VHDL 2008 example
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2016.4:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity top is
    port (
	top_clk : in std_logic;
	top_in : in std_logic;
	top_out : out std_logic;
	--
	int_rel_out : out std_logic;
	int_abs_out : out std_logic
    );
end entity top;

architecture RTL of top is

    signal sub_clk : std_logic;
    signal sub_in : std_logic;
    signal sub_out : std_logic;

    alias int_rel is << signal sub.intern : std_logic >>;
    alias int_abs is << signal .top.sub.intern : std_logic >>;

begin
    SUB_inst : entity work.sub
	port map (
	    clk => sub_clk,
	    data_in => sub_in,
	    data_out => sub_out );

    sub_clk <= top_clk;
    sub_in <= top_in;
    top_out <= sub_out;

    int_rel_out <= int_rel;
    int_abs_out <= int_abs;

end RTL;