----------------------------------------------------------------------------
--  sub.vhd
--	Simple VHDL 2008 example
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2016.4:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity sub is
    port (
	clk : in std_logic;
	data_in : in std_logic;
	data_out : out std_logic
    );
end entity sub;


architecture RTL of sub is

    signal intern : std_logic;

begin
    
    sub_proc : process (clk)
    begin
	if rising_edge(clk) then
	    data_out <= intern;
	    intern <= data_in;
	end if;
    end process;

end RTL;