----------------------------------------------------------------------------
--  vect_bias.vhd
--	Calculate Logic Vector Bias
--	Version 1.0
--
--  Copyright (C) 2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

use work.vivado_pkg.ALL;	-- Vivado Attributes
use work.reduce_pkg.ALL;	-- Logic Reduction


entity vect_bias is
    port (
	clk	: in std_logic;
	--
	din	: in std_logic_vector (7 downto 0);
	--
	bias	: out signed (3 downto 0)
   );
end entity vect_bias;



architecture RTL_PIPE of vect_bias is

    attribute KEEP_HIERARCHY of RTL_PIPE : architecture is "TRUE";

    signal and_p1 : std_logic_vector (3 downto 0);
    signal xor_p1 : std_logic_vector (3 downto 0);

    -- attribute DONT_TOUCH of and_p1 : signal is "TRUE";
    -- attribute DONT_TOUCH of xor_p1 : signal is "TRUE";

    signal and_sum_p2 : unsigned (2 downto 0);
    signal xor_sum_p2 : unsigned (2 downto 0);

    -- attribute DONT_TOUCH of and_sum_p2 : signal is "TRUE";
    -- attribute DONT_TOUCH of xor_sum_p2 : signal is "TRUE";

    signal sum_p3 : unsigned (3 downto 0);

begin

    add_proc0 : process (clk)
    begin
	if rising_edge(clk) then
	    for I in 0 to 3 loop
		and_p1(I) <= din(I * 2) and din(I * 2 + 1);
		xor_p1(I) <= din(I * 2) xor din(I * 2 + 1);
	    end loop;
	end if;
    end process;

    -- second level, add up and/xor
    add_proc : process (clk)
    begin
	if rising_edge(clk) then
	    and_sum_p2(2) <= and_reduce(and_p1);
	    and_sum_p2(1) <=
		or_reduce(and_p1(2 downto 0)) and
		or_reduce(and_p1(3 downto 1)) and
		(and_p1(0) or and_p1(1) or and_p1(3)) and
		(and_p1(0) or and_p1(2) or and_p1(3)) and
		not and_reduce(and_p1);
	    and_sum_p2(0) <= xor_reduce(and_p1);

	    xor_sum_p2(2) <= and_reduce(xor_p1);
	    xor_sum_p2(1) <=
		or_reduce(xor_p1(2 downto 0)) and
		or_reduce(xor_p1(3 downto 1)) and
		(xor_p1(0) or xor_p1(1) or xor_p1(3)) and
		(xor_p1(0) or xor_p1(2) or xor_p1(3)) and
		not and_reduce(xor_p1);
	    xor_sum_p2(0) <= xor_reduce(xor_p1);
	end if;
    end process;

    -- third level, combine
    combine_proc : process (clk)
    begin
	if rising_edge(clk) then
	    sum_p3 <= ('0' & xor_sum_p2) + (and_sum_p2 & '0');
	end if;
    end process;

    out_proc : process (clk)
    begin
	if rising_edge(clk) then
	    bias <= signed(sum_p3) - to_signed(4, 4);
	end if;
    end process;

end RTL_PIPE;


architecture RTL of vect_bias is

    attribute KEEP_HIERARCHY of RTL : architecture is "TRUE";

    signal ones : signed (3 downto 0);
    signal zeros : signed (3 downto 0);

    function count_bits_f (
	vec : std_logic_vector;
	val : std_logic )
	return natural is
	variable num : natural := 0;
    begin
	for I in vec'range loop
	    if vec(I) = val then
		num := num + 1;
	    end if;
	end loop;
	return num;
    end function;

begin

    bias_proc : process (clk)
	variable ones_v : natural range 0 to 8;
	variable zeros_v : natural range 0 to 8;
    begin
	if rising_edge(clk) then
	    ones_v := count_bits_f(din, '1');
	    zeros_v := count_bits_f(din, '0');

	    ones <= to_signed(ones_v, 4);
	    zeros <= to_signed(zeros_v, 4);

	    bias <= (ones - zeros) / 2;
	end if;
    end process;

end RTL;