----------------------------------------------------------------------------
--  top.vhd
--	Simple TMDS Test
--	Version 1.0
--
--  Copyright (C) 2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2014.1:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity top is
    port (
	clk	: in std_logic;
	--
	din0	: in std_logic_vector (7 downto 0);
	din1	: in std_logic_vector (7 downto 0);
	din2	: in std_logic_vector (7 downto 0);
	--
	dout0	: out std_logic_vector (15 downto 0);
	dout1	: out std_logic_vector (3 downto 0);
	dout2	: out std_logic_vector (23 downto 0)
    );
end entity top;


architecture RTL of top is

    signal din0_d : std_logic_vector (7 downto 0);
    signal din1_d : std_logic_vector (7 downto 0);
    signal din2_d : std_logic_vector (7 downto 0);

    signal xor_out0 : std_logic_vector (7 downto 0);
    signal xnor_out0 : std_logic_vector (7 downto 0);

    signal bias1 : signed (3 downto 0);

    signal xor_out2 : std_logic_vector (7 downto 0);
    signal xnor_out2 : std_logic_vector (7 downto 0);

    signal xor_bias2 : signed (3 downto 0);
    signal xnor_bias2 : signed (3 downto 0);

    signal dout0_d : std_logic_vector (15 downto 0);
    signal dout1_d : std_logic_vector (3 downto 0);
    signal dout2_d : std_logic_vector (23 downto 0);

begin

    register_proc0 : process (clk)
    begin
	if rising_edge(clk) then
	    din0_d <= din0;
	    din1_d <= din1;
	    din2_d <= din2;
	end if;
    end process;

    xor_xnor_inst0 : entity work.xor_xnor
	port map (
	    clk => clk,
	    --
	    din => din0_d,
	    --
	    xor_out => xor_out0,
	    xnor_out => xnor_out0 );

    dout0_d <= xor_out0 & xnor_out0;

    vect_bias_inst1 : entity work.vect_bias
	port map (
	    clk => clk,
	    --
	    din => din1_d,
	    --
	    bias => bias1 );

    dout1_d <= std_logic_vector(bias1);

    xor_xnor_inst2 : entity work.xor_xnor
	port map (
	    clk => clk,
	    --
	    din => din2_d,
	    --
	    xor_out => xor_out2,
	    xnor_out => xnor_out2 );

    vect_bias_inst2a : entity work.vect_bias
	port map (
	    clk => clk,
	    --
	    din => xor_out2,
	    --
	    bias => xor_bias2 );

    vect_bias_inst2b : entity work.vect_bias
	port map (
	    clk => clk,
	    --
	    din => xnor_out2,
	    --
	    bias => xnor_bias2 );

    dout2_d <= xor_out2 & xnor_out2 &
	std_logic_vector(xor_bias2) &
	std_logic_vector(xnor_bias2);

    register_proc1 : process (clk)
    begin
	if rising_edge(clk) then
	    dout0 <= dout0_d;
	    dout1 <= dout1_d;
	    dout2 <= dout2_d;
	end if;
    end process;

end RTL;