#----------------------------------------------------------- # Vivado v2014.1 (64-bit) # SW Build 881834 on Fri Apr 4 14:00:25 MDT 2014 # IP Build 877625 on Fri Mar 28 16:29:15 MDT 2014 # Start of session at: Tue May 6 05:24:59 2014 # Process ID: 8459 # Log file: /var/opt/AXIOM/PROJ/ZYBO/tmds_test/build.vivado/vivado.log # Journal file: /var/opt/AXIOM/PROJ/ZYBO/tmds_test/build.vivado/vivado.jou #----------------------------------------------------------- source ../vivado.tcl # set ODIR . # read_vhdl ../xor_xnor.vhd # read_vhdl ../vect_bias.vhd # read_vhdl ../vivado_pkg.vhd # read_vhdl ../top.vhd # read_xdc ../top.xdc # set_property PART xc7z010clg400-1 [current_project] # set_property TARGET_LANGUAGE VHDL [current_project] # synth_design -top top -flatten rebuilt Command: synth_design -top top -flatten rebuilt Starting synthesis... Using part: xc7z010clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 760.875 ; gain = 157.906 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.vhd:39] INFO: [Synth 8-638] synthesizing module 'xor_xnor' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/xor_xnor.vhd:34] INFO: [Synth 8-256] done synthesizing module 'xor_xnor' (1#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/xor_xnor.vhd:34] INFO: [Synth 8-638] synthesizing module 'vect_bias' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/vect_bias.vhd:33] INFO: [Synth 8-256] done synthesizing module 'vect_bias' (2#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/vect_bias.vhd:33] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.vhd:39] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 795.742 ; gain = 192.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Loading clock regions from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/ClockRegion.xml Loading clock buffers from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/ClockBuffers.xml Loading clock placement rules from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/ClockPlacerRules.xml Loading package pin functions from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/PinFunctions.xml... Loading package from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/clg400/Package.xml Loading io standards from /opt/Xilinx/Vivado/2014.1/data/./parts/xilinx/zynq/IOStandards.xml Processing XDC Constraints Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] Finished Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1007.082 ; gain = 404.113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1007.082 ; gain = 404.113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1007.082 ; gain = 404.113 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 3 3 Input 4 Bit Adders := 3 2 Input 4 Bit Adders := 42 +---XORs : 2 Input 1 Bit XORs := 28 +---Registers : 24 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 7 4 Bit Registers := 10 +---Muxes : 2 Input 4 Bit Muxes := 42 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 24 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 3 4 Bit Registers := 1 Module xor_xnor Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 14 +---Registers : 8 Bit Registers := 2 Module vect_bias Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 3 Input 4 Bit Adders := 1 2 Input 4 Bit Adders := 14 +---Registers : 4 Bit Registers := 3 +---Muxes : 2 Input 4 Bit Muxes := 14 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1070.090 ; gain = 467.121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[0] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\bias_reg[2] ) is unused and will be removed from module vect_bias. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[0] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout1_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[8] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[6] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[2] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[4] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[6] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[2] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[4] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[6] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[6] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[4] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[14] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[12] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[10] ) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias__1. WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias__2. WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |BUFG | 1| |2 |LUT2 | 4| |3 |LUT3 | 5| |4 |LUT4 | 18| |5 |LUT5 | 33| |6 |LUT6 | 28| |7 |FDRE | 111| |8 |IBUF | 25| |9 |OBUF | 44| +------+-----+------+ Report Instance Areas: +------+-------------------+-------------+------+ | |Instance |Module |Cells | +------+-------------------+-------------+------+ |1 |top | | 269| |2 | xor_xnor_inst0 |xor_xnor__1 | 23| |3 | vect_bias_inst1 |vect_bias__1 | 32| |4 | xor_xnor_inst2 |xor_xnor | 23| |5 | vect_bias_inst2a |vect_bias__2 | 32| |6 | vect_bias_inst2b |vect_bias | 32| +------+-------------------+-------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 22 warnings. Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.145 ; gain = 499.176 INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] Finished Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 15 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1106.141 ; gain = 397.262 # write_checkpoint -force $ODIR/post_synth # opt_design -directive Default Command: opt_design -directive Default INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Default Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1107.145 ; gain = 1.000 Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 13c9158ac Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.633 ; gain = 328.488 Phase 2 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-10] Eliminated 0 cells. Phase 2 Constant Propagation | Checksum: 10cc77e55 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.633 ; gain = 328.488 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 0 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 3 Sweep | Checksum: 1a8f2ea75 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.633 ; gain = 328.488 Ending Logic Optimization Task | Checksum: 1a8f2ea75 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.633 ; gain = 328.488 Implement Debug Cores | Checksum: 13c9158ac Logic Optimization | Checksum: 13c9158ac Starting Power Optimization Task Ending Power Optimization Task | Checksum: 1a8f2ea75 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.633 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.633 ; gain = 329.488 # place_design -directive Default Command: place_design -directive Default Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Default' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.637 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.637 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization | Checksum: 00000000 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1435.637 ; gain = 0.004 Phase 1.1.2 Build Super Logic Region (SLR) Database Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: 00000000 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1435.637 ; gain = 0.004 Phase 1.1.3 Add Constraints Phase 1.1.3 Add Constraints | Checksum: 00000000 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1435.637 ; gain = 0.004 Phase 1.1.4 Build Shapes/ HD Config Phase 1.1.4.1 Build Macros Phase 1.1.4.1 Build Macros | Checksum: caa1fb29 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.4 Build Shapes/ HD Config | Checksum: caa1fb29 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device Phase 1.1.5.1 Pre-Place Cells Phase 1.1.5.1 Pre-Place Cells | Checksum: 00000000 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.5.2 Implementation Feasibility check Phase 1.1.5.2 Implementation Feasibility check | Checksum: 00000000 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1459.645 ; gain = 24.012 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1.5.3 Implementation Feasibility check On IDelay Phase 1.1.5.3 Implementation Feasibility check On IDelay | Checksum: 00000000 Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14a153992 Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.6 Build Placer Netlist Model Phase 1.1.6.1 Place Init Design Phase 1.1.6.1.1 Build Clock Data Phase 1.1.6.1.1 Build Clock Data | Checksum: 22f9b73b1 Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.55 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.6.1 Place Init Design | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.6 Build Placer Netlist Model | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.7 Constrain Clocks/Macros Phase 1.1.7.1 Constrain Global/Regional Clocks Phase 1.1.7.1 Constrain Global/Regional Clocks | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1.7 Constrain Clocks/Macros | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1.1 Placer Initialization Core | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 1 Placer Initialization | Checksum: 1b613e1e4 Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 2 Global Placement Phase 2.1 Run Budgeter Phase 2.1 Run Budgeter | Checksum: 164ab8470 Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.67 . Memory (MB): peak = 1459.645 ; gain = 24.012 Phase 2 Global Placement | Checksum: 1d8b3f0e4 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.97 . Memory (MB): peak = 1467.648 ; gain = 32.016 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d8b3f0e4 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.97 . Memory (MB): peak = 1467.648 ; gain = 32.016 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18fec479d Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1467.648 ; gain = 32.016 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 248d29d65 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1467.648 ; gain = 32.016 Phase 3.4 Timing Path Optimizer Phase 3.4 Timing Path Optimizer | Checksum: 14c9de65c Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1467.648 ; gain = 32.016 Phase 3.5 Commit Small Macros & Core Logic Phase 3.5 Commit Small Macros & Core Logic | Checksum: 22f40bd58 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 22f40bd58 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 3 Detail Placement | Checksum: 22f40bd58 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 22f40bd58 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.2.1.2 updateTiming after Restore Best Placement Phase 4.2.1.2 updateTiming after Restore Best Placement | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.725. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.2 Post Placement Optimization | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.4 Placer Reporting | Checksum: 1f58e11ab Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 1ed042c2b Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ed042c2b Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 Ending Placer Task | Checksum: 1314d2ebc Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 48.023 # phys_opt_design -directive Default Command: phys_opt_design -directive Default Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Default Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization Phase 1 Physical Synthesis Initialization | Checksum: 218280388 Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1483.656 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.656 ; gain = 0.000 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.628 | TNS=-5.133 | Phase 2 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 2 Fanout Optimization | Checksum: 218280388 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 16 candidate nets for placement-based optimization. INFO: [Physopt 32-663] Processed net vect_bias_inst2a/ones[2]. Re-placed instance vect_bias_inst2a/ones_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_bias[1]_i_2. Did not re-place instance vect_bias_inst2a/bias[1]_i_2 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/bias1[3]. Did not re-place instance vect_bias_inst2a/bias[3]_i_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/bias4[3]. Did not re-place instance vect_bias_inst2a/bias[1]_i_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_bias[3]_i_2. Did not re-place instance vect_bias_inst2a/bias[3]_i_2 INFO: [Physopt 32-663] Processed net vect_bias_inst2b/ones[2]. Re-placed instance vect_bias_inst2b/ones_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2b/n_0_bias[0]_i_2. Did not re-place instance vect_bias_inst2b/bias[0]_i_2 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/n_0_bias[1]_i_2. Did not re-place instance vect_bias_inst2b/bias[1]_i_2 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/bias1[3]. Did not re-place instance vect_bias_inst2b/bias[3]_i_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/n_0_bias[0]_i_4. Did not re-place instance vect_bias_inst2b/bias[0]_i_4 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/n_0_bias[3]_i_2. Did not re-place instance vect_bias_inst2b/bias[3]_i_2 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/ones[1]. Did not re-place instance vect_bias_inst2b/ones_reg[1] INFO: [Physopt 32-662] Processed net vect_bias_inst2b/n_0_bias[0]_i_5. Did not re-place instance vect_bias_inst2b/bias[0]_i_5 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/bias4[3]. Did not re-place instance vect_bias_inst2b/bias[1]_i_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2b/bias[3]. Did not re-place instance vect_bias_inst2b/bias_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/bias[3]. Did not re-place instance vect_bias_inst2a/bias_reg[3] INFO: [Physopt 32-661] Optimized 2 nets. Re-placed 2 instances. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.590 | TNS=-5.625 | Phase 3 Placement Based Optimization | Checksum: 2014b3622 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 4 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-197] Pass 1. Identified 7 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net vect_bias_inst2b/n_0_bias[0]_i_2. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst2b/n_0_bias[0]_i_5. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst2a/n_0_bias[0]_i_2. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst2a/n_0_zeros[3]_i_3. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst1/n_0_bias[0]_i_5. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst1/n_0_bias[0]_i_2. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net vect_bias_inst2a/n_0_bias[0]_i_5. Rewired (signal push) vect_bias_inst2a/ones[1] to 1 loads. Replicated 1 times. INFO: [Physopt 32-29] End Pass 1. Optimized 1 net. Created 1 new instance. INFO: [Physopt 32-197] Pass 2. Identified 1 candidate net for rewire optimization. INFO: [Physopt 32-134] Processed net vect_bias_inst2a/n_0_bias[0]_i_5. Rewiring did not optimize the net. INFO: [Physopt 32-29] End Pass 2. Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-238] Finished Signal Push optimization... INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.590 | TNS=-5.593 | Phase 4 Rewire | Checksum: 17c39cfb8 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 5 Critical Cell Optimization INFO: [Physopt 32-46] Identified 32 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net vect_bias_inst2b/ones[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2b/n_0_bias[0]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2b/n_0_bias[1]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net xor_xnor_inst2/xor_out[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net vect_bias_inst2a/n_0_ones[3]_i_3. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst2a/n_0_ones[3]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net xor_xnor_inst2/xor_out[3]. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst2b/ones[2] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2a/ones[2] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-571] Net vect_bias_inst2a/n_0_bias[0]_i_2 was not replicated. INFO: [Physopt 32-572] Net vect_bias_inst2a/n_0_bias[1]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2b/zeros[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net vect_bias_inst2a/ones[1]. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst2a/ones[3] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net vect_bias_inst2a/n_0_zeros[3]_i_3. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst2a/zeros[3] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net xor_xnor_inst2/xnor_out[5]. Replicated 1 times. INFO: [Physopt 32-601] Processed net vect_bias_inst2b/n_0_ones[3]_i_3. Net driver vect_bias_inst2b/ones[3]_i_3 was replaced. INFO: [Physopt 32-572] Net vect_bias_inst2a/zeros[2] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net xor_xnor_inst2/xnor_out[3]. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst2b/zeros[2] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net xor_xnor_inst2/xnor_out[7] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2a/zeros[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst1/ones[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst1/n_0_bias[0]_i_5 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst1/n_0_bias[1]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net vect_bias_inst2b/n_0_ones[3]_i_2. Net driver vect_bias_inst2b/ones[3]_i_2 was replaced. INFO: [Physopt 32-81] Processed net vect_bias_inst1/zeros[1]. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst1/n_0_bias[0]_i_2 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net xor_xnor_inst2/xor_out[7]. Replicated 1 times. INFO: [Physopt 32-572] Net vect_bias_inst1/zeros[2] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 11 nets. Created 9 new instances. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.590 | TNS=-8.216 | Phase 5 Critical Cell Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 6 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 6 DSP Register Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 7 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 7 BRAM Register Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 8 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 8 Shift Register Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 9 Critical Pin Optimization INFO: [Physopt 32-606] Identified 8 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 0 net. Swapped 0 pin. Phase 9 Critical Pin Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 10 Very High Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 10 Very High Fanout Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Phase 11 BRAM Enable Optimization Phase 11 BRAM Enable Optimization | Checksum: 1de4bfd69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.656 ; gain = 0.000 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.590 | TNS=-8.216 | Ending Physical Synthesis Task | Checksum: 1e7e435b5 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 80 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1483.656 ; gain = 0.000 # write_checkpoint -force $ODIR/post_place Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1483.660 ; gain = 0.000 # route_design -directive Default Command: route_design -directive Default Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Default'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 4ba181f6 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1557.656 ; gain = 67.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 4ba181f6 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1557.660 ; gain = 67.004 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 190892d8e Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.652 | TNS=-11.1 | WHS=-0.096 | THS=-1.44 | Phase 2 Router Initialization | Checksum: 190892d8e Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: e141f048 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: dc8e9258 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.97 | TNS=-16.1 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 15e86eeb2 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 15e86eeb2 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.1.2 GlobIterForTiming | Checksum: 118c00531 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.1 Global Iteration 0 | Checksum: 118c00531 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 11db1da93 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.802 | TNS=-15.6 | WHS=N/A | THS=N/A | Phase 4.2.2 GlobIterForTiming Phase 4.2.2.1 Update Timing Phase 4.2.2.1 Update Timing | Checksum: 7f0d1a8b Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.2.2.2 Fast Budgeting Phase 4.2.2.2 Fast Budgeting | Checksum: 7f0d1a8b Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.2.2 GlobIterForTiming | Checksum: 10e34edc5 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.2 Global Iteration 1 | Checksum: 10e34edc5 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 33 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.3.1 Update Timing Phase 4.3.1 Update Timing | Checksum: 10108f806 Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.84 | TNS=-15.7 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: ef8a4b8c Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 4 Rip-up And Reroute | Checksum: ef8a4b8c Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: ef8a4b8c Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.653 | TNS=-10.3 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1577.656 ; gain = 87.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.652 | TNS=-9.77 | WHS=0.102 | THS=0 | Phase 7 Post Hold Fix | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.226914 % Global Horizontal Routing Utilization = 0.128217 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. Phase 8 Route finalize | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1577.656 ; gain = 87.000 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 65a556b3 Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1579.656 ; gain = 89.000 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 9d0869bc Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1579.656 ; gain = 89.000 Phase 11 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.652 | TNS=-9.77 | WHS=0.102 | THS=0 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 11 Post Router Timing | Checksum: 9d0869bc Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1579.656 ; gain = 89.000 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 9d0869bc Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1579.656 ; gain = 89.000 Routing Is Done. Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1581.867 ; gain = 91.211 INFO: [Common 17-83] Releasing license: Implementation 15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:16 . Memory (MB): peak = 1581.867 ; gain = 98.207 # place_design -post_place_opt Command: place_design -post_place_opt Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.1 Build Super Logic Region (SLR) Database Phase 1.1.1 Build Super Logic Region (SLR) Database | Checksum: eda6af08 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.2 Add Constraints Phase 1.1.2 Add Constraints | Checksum: eda6af08 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.3 Build Macros Phase 1.1.3 Build Macros | Checksum: e1e32ca6 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.4 Implementation Feasibility check Phase 1.1.4 Implementation Feasibility check | Checksum: e1e32ca6 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5 Placer Initialization Phase 1.1.5.1 Build Placer Netlist Model Phase 1.1.5.1.1 Place Init Design Phase 1.1.5.1.1.1 Build Clock Data Phase 1.1.5.1.1.1 Build Clock Data | Checksum: 1663c72a5 Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5.1.1 Place Init Design | Checksum: 107dd65aa Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5.1 Build Placer Netlist Model | Checksum: 107dd65aa Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros Phase 1.1.5.2.1 Constrain Global/Regional Clocks Phase 1.1.5.2.1 Constrain Global/Regional Clocks | Checksum: 107dd65aa Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros | Checksum: 107dd65aa Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1.5 Placer Initialization | Checksum: 107dd65aa Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1.1 Placer Initialization Core | Checksum: 107dd65aa Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 107dd65aa Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 2 Constrain Global/Regional Clocks Phase 2 Constrain Global/Regional Clocks | Checksum: 107dd65aa Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 107dd65aa Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 3.2 Commit Small Macros & Core Logic Phase 3.2 Commit Small Macros & Core Logic | Checksum: 23d7dad61 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 23d7dad61 Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 23d7dad61 Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.2.1.2 updateTiming after Restore Best Placement Phase 4.2.1.2 updateTiming after Restore Best Placement | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.573. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.2 Post Placement Optimization | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.4 Placer Reporting | Checksum: 1c3eaa1b7 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 1cfae2419 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1cfae2419 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 Ending Placer Task | Checksum: 1baf37d69 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1581.867 ; gain = 0.000 # phys_opt_design Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization Phase 1 Physical Synthesis Initialization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.573 | TNS=-7.139 | Phase 2 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 2 Fanout Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 1 candidate net for placement-based optimization. INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[3]. Did not re-place instance vect_bias_inst2a/ones_reg[3] INFO: [Physopt 32-661] Optimized 0 nets. Re-placed 0 instances. Phase 3 Placement Based Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 4 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 4 Rewire | Checksum: 2b5310416 Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 5 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 5 Critical Cell Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 6 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 6 DSP Register Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 7 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 7 BRAM Register Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 8 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 8 Shift Register Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 9 Critical Pin Optimization INFO: [Physopt 32-606] Identified 1 candidate net for critical-pin optimization. INFO: [Physopt 32-608] Optimized 0 net. Swapped 0 pin. Phase 9 Critical Pin Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 10 Very High Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 10 Very High Fanout Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 11 BRAM Enable Optimization Phase 11 BRAM Enable Optimization | Checksum: 2b5310416 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1581.867 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.573 | TNS=-7.139 | Ending Physical Synthesis Task | Checksum: 2b5310416 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1581.867 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: b189410a Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1581.867 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: b189410a Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1581.867 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: a3794062 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.719 ; gain = 9.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.63 | TNS=-9.86 | WHS=-0.138 | THS=-1.73 | Phase 2 Router Initialization | Checksum: a3794062 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 127f67eeb Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 1dae5855c Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1591.719 ; gain = 9.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.683 | TNS=-12.7 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: c5a1e8d5 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: c5a1e8d5 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4.1.2 GlobIterForTiming | Checksum: 14870696a Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4.1 Global Iteration 0 | Checksum: 14870696a Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 4 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X23Y36/IMUX30 Overlapping nets: 2 vect_bias_inst2b/n_0_bias[0]_i_5 vect_bias_inst2b/zeros[2] 2. INT_R_X23Y33/IMUX16 Overlapping nets: 2 vect_bias_inst2a/ones[2] vect_bias_inst2a/zeros[2] 3. INT_L_X24Y35/IMUX_L17 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[7]_repN 4. INT_R_X23Y35/SR1BEG2 Overlapping nets: 2 xor_xnor_inst2/xor_out[5]_repN vect_bias_inst2a/n_0_zeros[3]_i_2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 109a25530 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1591.719 ; gain = 9.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.683 | TNS=-12.5 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 109a25530 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 4 Rip-up And Reroute | Checksum: 109a25530 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1591.719 ; gain = 9.852 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 109a25530 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1591.719 ; gain = 9.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.568 | TNS=-7.32 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1592.719 ; gain = 10.852 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1592.719 ; gain = 10.852 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1592.719 ; gain = 10.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.553 | TNS=-6.62 | WHS=0.102 | THS=0 | Phase 7 Post Hold Fix | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1592.719 ; gain = 10.852 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.225929 % Global Horizontal Routing Utilization = 0.139017 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. Phase 8 Route finalize | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1592.719 ; gain = 10.852 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1fc813208 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1498494fc Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 Phase 11 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.553 | TNS=-6.62 | WHS=0.102 | THS=0 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 11 Post Router Timing | Checksum: 1498494fc Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 1498494fc Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 Routing Is Done. Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.719 ; gain = 12.852 # write_checkpoint -force $ODIR/post_route Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1594.723 ; gain = 0.000 # report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type max -sort_by slack. Startpoint Endpoint Slack ------------------------------------------------------------------- vect_bias_inst2b/ones_reg[1]/C vect_bias_inst2b/bias_reg[3]/D -0.551 vect_bias_inst2a/zeros_reg[3]/C vect_bias_inst2a/bias_reg[3]/D -0.451 vect_bias_inst1/ones_reg[1]/C vect_bias_inst1/bias_reg[3]/D -0.441 xor_xnor_inst2/xor_out_reg[5]_replica/C vect_bias_inst2a/ones_reg[1]/D -0.376 din2_d_reg[5]/C xor_xnor_inst2/xor_out_reg[6]/D -0.323 xor_xnor_inst2/xor_out_reg[4]/C vect_bias_inst2a/zeros_reg[3]/D -0.315 vect_bias_inst2b/ones_reg[1]/C vect_bias_inst2b/bias_reg[1]/D -0.300 vect_bias_inst2a/zeros_reg[3]/C vect_bias_inst2a/bias_reg[1]/D -0.295 din2_d_reg[4]/C xor_xnor_inst2/xor_out_reg[7]_replica/D -0.278 xor_xnor_inst2/xor_out_reg[7]/C vect_bias_inst2a/ones_reg[2]/D -0.265 xor_xnor_inst2/xor_out_reg[4]/C vect_bias_inst2b/ones_reg[2]/D -0.221 din2_d_reg[5]/C xor_xnor_inst2/xor_out_reg[5]_replica/D -0.206 xor_xnor_inst2/xnor_out_reg[3]_replica/C vect_bias_inst2b/zeros_reg[2]/D -0.194 xor_xnor_inst2/xor_out_reg[2]/C vect_bias_inst2b/ones_reg[3]/D -0.192 xor_xnor_inst2/xnor_out_reg[7]/C vect_bias_inst2b/zeros_reg[3]/D -0.187 xor_xnor_inst2/xor_out_reg[7]/C vect_bias_inst2a/ones_reg[3]/D -0.186 vect_bias_inst1/ones_reg[1]/C vect_bias_inst1/bias_reg[1]/D -0.170 xor_xnor_inst2/xnor_out_reg[7]/C vect_bias_inst2b/ones_reg[1]/D -0.162 din1_d_reg[2]/C vect_bias_inst1/zeros_reg[1]_replica/D -0.161 xor_xnor_inst2/xor_out_reg[4]/C vect_bias_inst2a/zeros_reg[1]/D -0.160 din1_d_reg[4]/C vect_bias_inst1/ones_reg[1]/D -0.137 din2_d_reg[2]/C xor_xnor_inst2/xor_out_reg[7]/D -0.133 xor_xnor_inst2/xor_out_reg[3]/C vect_bias_inst2a/zeros_reg[0]/D -0.120 vect_bias_inst2a/ones_reg[1]_replica/C vect_bias_inst2a/bias_reg[0]/D -0.120 din2_d_reg[5]/C xor_xnor_inst2/xnor_out_reg[5]/D -0.112 xor_xnor_inst2/xor_out_reg[4]/C vect_bias_inst2a/zeros_reg[2]/D -0.105 din1_d_reg[4]/C vect_bias_inst1/zeros_reg[3]/D -0.087 din1_d_reg[4]/C vect_bias_inst1/ones_reg[2]/D -0.073 din2_d_reg[0]/C xor_xnor_inst2/xnor_out_reg[5]_replica/D -0.052 xor_xnor_inst2/xnor_out_reg[7]/C vect_bias_inst2b/zeros_reg[0]/D -0.040 din1_d_reg[5]/C vect_bias_inst1/ones_reg[3]/D -0.029 xor_xnor_inst2/xnor_out_reg[7]/C vect_bias_inst2b/zeros_reg[1]/D -0.027 din1_d_reg[4]/C vect_bias_inst1/zeros_reg[2]/D -0.019 vect_bias_inst1/zeros_reg[3]/C vect_bias_inst1/bias_reg[0]/D -0.017 vect_bias_inst2b/zeros_reg[2]/C vect_bias_inst2b/bias_reg[0]/D -0.002 # report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type min -sort_by slack. INFO: [Timing 38-72] No paths found. No timing paths found. # report_pulse_width -significant_digits 3 -all_violators INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- | Tool Version : Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 | Date : Tue May 6 05:26:51 2014 | Host : neuromancer.lan running 64-bit Mageia 2 | Command : report_pulse_width -significant_digits 3 -all_violators | Design : top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.10 2014-03-13 ----------------------------------------------------------------------------------- Pulse Width Report start_gui report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -name timing_1 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs