#----------------------------------------------------------- # Vivado v2014.1 (64-bit) # SW Build 881834 on Fri Apr 4 14:00:25 MDT 2014 # IP Build 877625 on Fri Mar 28 16:29:15 MDT 2014 # Start of session at: Tue May 6 05:00:46 2014 # Process ID: 6643 # Log file: /var/opt/AXIOM/PROJ/ZYBO/tmds_test/build.vivado/vivado.log # Journal file: /var/opt/AXIOM/PROJ/ZYBO/tmds_test/build.vivado/vivado.jou #----------------------------------------------------------- source ../vivado.tcl # set ODIR . # read_vhdl ../xor_xnor.vhd # read_vhdl ../vect_bias.vhd # read_vhdl ../vivado_pkg.vhd # read_vhdl ../top.vhd # read_xdc ../top.xdc # set_property PART xc7z010clg400-1 [current_project] # set_property TARGET_LANGUAGE VHDL [current_project] # synth_design -top top -flatten rebuilt Command: synth_design -top top -flatten rebuilt Starting synthesis... Using part: xc7z010clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 760.871 ; gain = 157.906 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.vhd:39] INFO: [Synth 8-638] synthesizing module 'xor_xnor' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/xor_xnor.vhd:34] INFO: [Synth 8-256] done synthesizing module 'xor_xnor' (1#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/xor_xnor.vhd:34] INFO: [Synth 8-638] synthesizing module 'vect_bias' [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/vect_bias.vhd:33] INFO: [Synth 8-256] done synthesizing module 'vect_bias' (2#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/vect_bias.vhd:33] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.vhd:39] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 795.738 ; gain = 192.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Loading clock regions from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/ClockRegion.xml Loading clock buffers from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/ClockBuffers.xml Loading clock placement rules from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/ClockPlacerRules.xml Loading package pin functions from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/PinFunctions.xml... Loading package from /opt/Xilinx/Vivado/2014.1/data/parts/xilinx/zynq/zynq/xc7z010/clg400/Package.xml Loading io standards from /opt/Xilinx/Vivado/2014.1/data/./parts/xilinx/zynq/IOStandards.xml Processing XDC Constraints Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] WARNING: [Place 30-481] SLICE_X41Y1:SLICE_X41Y34 doesn't align to a tile boundary on these sides: west, Tile includes these sites: SLICE_X40Y1:SLICE_X41Y34. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:94] WARNING: [Place 30-481] SLICE_X42Y15:SLICE_X42Y49 doesn't align to a tile boundary on these sides: east, Tile includes these sites: SLICE_X42Y15:SLICE_X43Y49. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:99] WARNING: [Place 30-481] SLICE_X40Y15:SLICE_X40Y49 doesn't align to a tile boundary on these sides: east, Tile includes these sites: SLICE_X40Y15:SLICE_X41Y49. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:104] Finished Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this message, exclude constraints listed in [.Xil/top_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1007.078 ; gain = 404.113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1007.078 ; gain = 404.113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1007.078 ; gain = 404.113 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 3 3 Input 4 Bit Adders := 3 2 Input 4 Bit Adders := 42 +---XORs : 2 Input 1 Bit XORs := 28 +---Registers : 24 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 7 4 Bit Registers := 10 +---Muxes : 2 Input 4 Bit Muxes := 42 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 24 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 3 4 Bit Registers := 1 Module xor_xnor Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 14 +---Registers : 8 Bit Registers := 2 Module vect_bias Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 3 Input 4 Bit Adders := 1 2 Input 4 Bit Adders := 14 +---Registers : 4 Bit Registers := 3 +---Muxes : 2 Input 4 Bit Muxes := 14 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 1072.086 ; gain = 469.121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[0] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\bias_reg[2] ) is unused and will be removed from module vect_bias. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[0] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout1_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[8] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[6] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[2] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[4] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[6] ) is unused and will be removed from module xor_xnor__1. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[2] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[4] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\xnor_out_reg[6] ) is unused and will be removed from module xor_xnor. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[6] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[4] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout0_reg[2] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[14] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[12] ) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (\dout2_reg[10] ) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias__1. WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias__2. WARNING: [Synth 8-3332] Sequential element (\ones_reg[0] ) is unused and will be removed from module vect_bias. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |BUFG | 1| |2 |LUT2 | 4| |3 |LUT3 | 5| |4 |LUT4 | 18| |5 |LUT5 | 33| |6 |LUT6 | 28| |7 |FDRE | 111| |8 |IBUF | 25| |9 |OBUF | 44| +------+-----+------+ Report Instance Areas: +------+-------------------+-------------+------+ | |Instance |Module |Cells | +------+-------------------+-------------+------+ |1 |top | | 269| |2 | xor_xnor_inst0 |xor_xnor__1 | 23| |3 | vect_bias_inst1 |vect_bias__1 | 32| |4 | xor_xnor_inst2 |xor_xnor | 23| |5 | vect_bias_inst2a |vect_bias__2 | 32| |6 | vect_bias_inst2b |vect_bias | 32| +------+-------------------+-------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 22 warnings. Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 1103.137 ; gain = 500.172 INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] WARNING: [Place 30-481] SLICE_X41Y1:SLICE_X41Y34 doesn't align to a tile boundary on these sides: west, Tile includes these sites: SLICE_X40Y1:SLICE_X41Y34. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:94] WARNING: [Place 30-481] SLICE_X42Y15:SLICE_X42Y49 doesn't align to a tile boundary on these sides: east, Tile includes these sites: SLICE_X42Y15:SLICE_X43Y49. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:99] WARNING: [Place 30-481] SLICE_X40Y15:SLICE_X40Y49 doesn't align to a tile boundary on these sides: east, Tile includes these sites: SLICE_X40Y15:SLICE_X41Y49. [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc:104] Finished Parsing XDC File [/var/opt/AXIOM/PROJ/ZYBO/tmds_test/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 16 Infos, 28 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1106.129 ; gain = 397.254 # write_checkpoint -force $ODIR/post_synth Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1106.133 ; gain = 0.000 # opt_design -directive ExploreSequentialArea Command: opt_design -directive ExploreSequentialArea INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreSequentialArea Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1107.133 ; gain = 1.000 Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1b82a1135 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.621 ; gain = 328.488 Phase 2 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-10] Eliminated 0 cells. Phase 2 Constant Propagation | Checksum: 1886036de Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.621 ; gain = 328.488 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 0 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 3 Sweep | Checksum: 2248ba2fe Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1435.621 ; gain = 328.488 Phase 4 Resynthesis INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-74] Optimized 3 modules. INFO: [Opt 31-75] Optimized module 'vect_bias'. INFO: [Opt 31-75] Optimized module 'vect_bias__1'. INFO: [Opt 31-75] Optimized module 'vect_bias__2'. INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-95] Resynthesis added 42 cells. INFO: [Opt 31-12] Eliminated 36 unconnected nets. INFO: [Opt 31-11] Eliminated 75 unconnected cells. INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-10] Eliminated 0 cells. INFO: [Opt 31-12] Eliminated 0 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 4 Resynthesis | Checksum: 138e93cb1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1439.535 ; gain = 332.402 Phase 5 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-10] Eliminated 0 cells. Phase 5 Constant Propagation | Checksum: 138e93cb1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1439.535 ; gain = 332.402 Phase 6 Sweep INFO: [Opt 31-12] Eliminated 0 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 6 Sweep | Checksum: 138e93cb1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1439.535 ; gain = 332.402 Ending Logic Optimization Task | Checksum: 138e93cb1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1439.535 ; gain = 332.402 Implement Debug Cores | Checksum: 1b82a1135 Logic Optimization | Checksum: 1b82a1135 Starting Power Optimization Task Ending Power Optimization Task | Checksum: 138e93cb1 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1439.535 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 31 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1439.535 ; gain = 333.402 # place_design -directive ExtraNetDelay_high Command: place_design -directive ExtraNetDelay_high Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraNetDelay_high' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1439.535 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1439.535 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization | Checksum: 7b98b889 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1439.535 ; gain = 0.000 Phase 1.1.2 Build Super Logic Region (SLR) Database Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: 7b98b889 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1439.535 ; gain = 0.000 Phase 1.1.3 Add Constraints Phase 1.1.3 Add Constraints | Checksum: f6744166 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1439.535 ; gain = 0.000 Phase 1.1.4 Build Shapes/ HD Config Phase 1.1.4.1 Build Macros Phase 1.1.4.1 Build Macros | Checksum: 158df45bc Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.4 Build Shapes/ HD Config | Checksum: 158df45bc Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device Phase 1.1.5.1 Pre-Place Cells Phase 1.1.5.1 Pre-Place Cells | Checksum: f6744166 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.5.2 Implementation Feasibility check Phase 1.1.5.2 Implementation Feasibility check | Checksum: f6744166 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1459.633 ; gain = 20.098 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1.5.3 Implementation Feasibility check On IDelay Phase 1.1.5.3 Implementation Feasibility check On IDelay | Checksum: f6744166 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device | Checksum: de5dd2b5 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.6 Build Placer Netlist Model Phase 1.1.6.1 Place Init Design Phase 1.1.6.1.1 Build Clock Data Phase 1.1.6.1.1 Build Clock Data | Checksum: 12b6d3d22 Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1459.633 ; gain = 20.098 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1.1.6.1 Place Init Design | Checksum: 110d80f14 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.6 Build Placer Netlist Model | Checksum: 110d80f14 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.7 Constrain Clocks/Macros Phase 1.1.7.1 Constrain Global/Regional Clocks Phase 1.1.7.1 Constrain Global/Regional Clocks | Checksum: 110d80f14 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1.7 Constrain Clocks/Macros | Checksum: 17f58d336 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1.1 Placer Initialization Core | Checksum: 17f58d336 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 1 Placer Initialization | Checksum: 17f58d336 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1459.633 ; gain = 20.098 Phase 2 Global Placement Phase 2.1 Run Budgeter Phase 2.1 Run Budgeter | Checksum: 18cc32dad Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 2 Global Placement | Checksum: 236a26807 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 236a26807 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 176a7772a Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22ffcb1d4 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 3.4 Timing Path Optimizer Phase 3.4 Timing Path Optimizer | Checksum: 1b8fa0dcc Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.81 . Memory (MB): peak = 1467.637 ; gain = 28.102 Phase 3.5 Commit Small Macros & Core Logic Phase 3.5 Commit Small Macros & Core Logic | Checksum: 1fa891b21 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.93 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 3.6 Detailed Placement of Flops Phase 3.6 Detailed Placement of Flops | Checksum: 22c47be94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 3.7 Place Remaining Phase 3.7 Place Remaining | Checksum: 22c47be94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 3.8 Re-assign LUT pins Phase 3.8 Re-assign LUT pins | Checksum: 22c47be94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.95 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 3 Detail Placement | Checksum: 22c47be94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.95 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 22c47be94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.2.1.2 updateTiming after Restore Best Placement Phase 4.2.1.2 updateTiming after Restore Best Placement | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.126. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.2 Post Placement Optimization | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.4 Placer Reporting | Checksum: 2d509b827 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 334b6c97a Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 334b6c97a Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 Ending Placer Task | Checksum: 29a0482a0 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1483.645 ; gain = 44.109 # phys_opt_design -directive ExploreWithHoldFix Command: phys_opt_design -directive ExploreWithHoldFix Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1 Physical Synthesis Initialization | Checksum: 25121742b Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1483.645 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.645 ; gain = 0.000 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-0.341 | Phase 2 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 2 Fanout Optimization | Checksum: 25121742b Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 21 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[6]. Did not re-place instance xor_xnor_inst2/xor_out_reg[6] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5 INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[7]. Did not re-place instance xor_xnor_inst2/xor_out_reg[7] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_4. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_4 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_2 INFO: [Physopt 32-662] Processed net vect_bias_inst1/vect_bias__1_net_2. Did not re-place instance vect_bias_inst1/vect_bias__1_LUT6_2 INFO: [Physopt 32-662] Processed net vect_bias_inst1/n_0_ones[3]_i_1. Did not re-place instance vect_bias_inst1/vect_bias__1_LUT5_1 INFO: [Physopt 32-663] Processed net din1_d[5]. Re-placed instance din1_d_reg[5] INFO: [Physopt 32-662] Processed net vect_bias_inst1/n_0_ones[2]_i_1. Did not re-place instance vect_bias_inst1/vect_bias__1_LUT5 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_3. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_3 INFO: [Physopt 32-663] Processed net din1_d[6]. Re-placed instance din1_d_reg[6] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[3]. Did not re-place instance vect_bias_inst2a/ones_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst1/ones[3]. Did not re-place instance vect_bias_inst1/ones_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[3]. Did not re-place instance vect_bias_inst2a/zeros_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst1/ones[2]. Did not re-place instance vect_bias_inst1/ones_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[2]. Did not re-place instance vect_bias_inst2a/zeros_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[2]. Did not re-place instance vect_bias_inst2a/ones_reg[2] INFO: [Physopt 32-661] Optimized 2 nets. Re-placed 2 instances. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-0.268 | Phase 3 Placement Based Optimization | Checksum: 21263687c Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 4 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-197] Pass 1. Identified 3 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net vect_bias_inst2a/vect_bias__2_net_1. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst1/vect_bias__1_net_1. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net vect_bias_inst2b/vect_bias_net_1. Rewiring did not optimize the net. INFO: [Physopt 32-29] End Pass 1. Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-238] Finished Signal Push optimization... Phase 4 Rewire | Checksum: 2a1704682 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 5 Critical Cell Optimization INFO: [Physopt 32-46] Identified 23 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net vect_bias_inst2a/vect_bias__2_net was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net xor_xnor_inst2/xor_out[7] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net vect_bias_inst2a/vect_bias__2_net_4. Net driver vect_bias_inst2a/vect_bias__2_LUT6_4 was replaced. INFO: [Physopt 32-572] Net vect_bias_inst2a/vect_bias__2_net_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net vect_bias_inst2a/vect_bias__2_net_3 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-571] Net vect_bias_inst1/vect_bias__1_net_1 was not replicated. INFO: [Physopt 32-571] Net din1_d[7] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2b/vect_bias_net_1 was not replicated. INFO: [Physopt 32-571] Net xor_xnor_inst2/xnor_out[7] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2b/vect_bias_net was not replicated. INFO: [Physopt 32-571] Net din1_d[6] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst1/vect_bias__1_net was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2b/vect_bias_net_2 was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2b/vect_bias_net_4 was not replicated. INFO: [Physopt 32-571] Net xor_xnor_inst2/xnor_out[5] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2a/vect_bias__2_net_2 was not replicated. INFO: [Physopt 32-571] Net din1_d[5] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst1/vect_bias__1_net_4 was not replicated. INFO: [Physopt 32-571] Net din1_d[4] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst1/vect_bias__1_net_3 was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst1/vect_bias__1_net_2 was not replicated. INFO: [Physopt 32-571] Net xor_xnor_inst2/xor_out[4] was not replicated. INFO: [Physopt 32-571] Net vect_bias_inst2b/vect_bias_net_3 was not replicated. INFO: [Physopt 32-232] Optimized 1 net. Created 0 new instance. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-0.264 | Phase 5 Critical Cell Optimization | Checksum: 228a464b9 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 6 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 6 Fanout Optimization | Checksum: 228a464b9 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 7 Placement Based Optimization INFO: [Physopt 32-660] Identified 14 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[6]. Did not re-place instance xor_xnor_inst2/xor_out_reg[6] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_4. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_4 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_1 INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[7]. Did not re-place instance xor_xnor_inst2/xor_out_reg[7] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_2 INFO: [Physopt 32-663] Processed net vect_bias_inst2a/vect_bias__2_net_3. Re-placed instance vect_bias_inst2a/vect_bias__2_LUT6_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[3]. Did not re-place instance vect_bias_inst2a/ones_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[3]. Did not re-place instance vect_bias_inst2a/zeros_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[2]. Did not re-place instance vect_bias_inst2a/zeros_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[2]. Did not re-place instance vect_bias_inst2a/ones_reg[2] INFO: [Physopt 32-661] Optimized 1 net. Re-placed 1 instance. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-0.264 | Phase 7 Placement Based Optimization | Checksum: 228a464b9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 8 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 8 Rewire | Checksum: 228a464b9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 9 Critical Cell Optimization INFO: [Physopt 32-46] Identified 3 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net xor_xnor_inst2/xor_out[7] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-571] Net vect_bias_inst2a/vect_bias__2_net_3 was not replicated. INFO: [Physopt 32-571] Net xor_xnor_inst2/xor_out[5] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. Phase 9 Critical Cell Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 10 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 10 Fanout Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 11 Placement Based Optimization INFO: [Physopt 32-660] Identified 13 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[6]. Did not re-place instance xor_xnor_inst2/xor_out_reg[6] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_1 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_ones[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_4. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_4 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[3]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_3 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/vect_bias__2_net_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT6_1 INFO: [Physopt 32-662] Processed net xor_xnor_inst2/xor_out[7]. Did not re-place instance xor_xnor_inst2/xor_out_reg[7] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/n_0_zeros[2]_i_1. Did not re-place instance vect_bias_inst2a/vect_bias__2_LUT5_2 INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[3]. Did not re-place instance vect_bias_inst2a/ones_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[3]. Did not re-place instance vect_bias_inst2a/zeros_reg[3] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/zeros[2]. Did not re-place instance vect_bias_inst2a/zeros_reg[2] INFO: [Physopt 32-662] Processed net vect_bias_inst2a/ones[2]. Did not re-place instance vect_bias_inst2a/ones_reg[2] INFO: [Physopt 32-661] Optimized 0 nets. Re-placed 0 instances. Phase 11 Placement Based Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 12 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 12 Rewire | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 13 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 13 Critical Cell Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 14 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 14 DSP Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 15 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 15 BRAM Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 16 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 16 Shift Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 17 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 17 DSP Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 18 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 18 BRAM Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 19 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 19 Shift Register Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 20 Critical Pin Optimization INFO: [Physopt 32-606] Identified 3 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 0 net. Swapped 0 pin. Phase 20 Critical Pin Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 21 Very High Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 21 Very High Fanout Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 22 BRAM Enable Optimization Phase 22 BRAM Enable Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Phase 23 Hold Fix Optimization INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.074 | TNS=-0.264 | WHS=0.131 | THS=0.000 | INFO: [Physopt 32-66] No high hold slack nets found for hold slack optimization. INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.074 | TNS=-0.264 | WHS=0.131 | THS=0.000 | Phase 23 Hold Fix Optimization | Checksum: 20ce5dade Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.645 ; gain = 0.000 INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.074 | TNS=-0.264 | WHS=0.131 | THS=0.000 | Ending Physical Synthesis Task | Checksum: 21263687c Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 119 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1483.645 ; gain = 0.000 # write_checkpoint -force $ODIR/post_place Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1483.648 ; gain = 0.000 # route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 107937f14 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1558.645 ; gain = 70.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 107937f14 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1558.648 ; gain = 70.004 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: ec97eb1c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.163 | TNS=-0.984 | WHS=-0.133 | THS=-2.31 | Phase 2 Router Initialization | Checksum: ec97eb1c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 11b7c76c1 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 59 Number of Nodes with overlaps = 50 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y17/IMUX4 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[4] 2. INT_R_X29Y17/IMUX43 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[4] 3. INT_L_X28Y15/IMUX_L38 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xnor_out[5] 4. INT_L_X28Y16/NE2BEG2 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[6] Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 1048617e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.232 | TNS=-2.16 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 79c78b13 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 79c78b13 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4.1.2 GlobIterForTiming | Checksum: 1c181f330 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4.1 Global Iteration 0 | Checksum: 1c181f330 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 29 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_L_X28Y15/IMUX_L35 Overlapping nets: 2 xor_xnor_inst2/xnor_out[3] xor_xnor_inst2/xor_out[4] Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 1d970f4b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.299 | TNS=-1.92 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1048617e7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 4 Rip-up And Reroute | Checksum: 1048617e7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 1048617e7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0794| TNS=-0.241 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0654| TNS=-0.217 | WHS=0.105 | THS=0 | Phase 7 Post Hold Fix | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0654| TNS=-0.217 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0864302 % Global Horizontal Routing Utilization = 0.0537684 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 11.7117%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 9 Route finalize | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1579.645 ; gain = 91.000 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 155d33568 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1581.645 ; gain = 93.000 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 140c298ab Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1581.645 ; gain = 93.000 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1581.645 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.095. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 140c298ab Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.645 ; gain = 93.000 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: 17d9e1727 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.645 ; gain = 93.000 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: 17d9e1727 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1581.648 ; gain = 93.004 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 18e2774be Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.178 | TNS=-1.21 | WHS=-0.133 | THS=-2.62 | Phase 14 Router Initialization | Checksum: 18e2774be Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 16a8508e6 Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 59 Number of Nodes with overlaps = 47 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y54/IMUX38 Overlapping nets: 2 din1_d[4] din1_d[3] 2. INT_L_X28Y15/IMUX_L38 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[4] Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: ac1d243f Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.28 | TNS=-2.38 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 1bc79df35 Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 1bc79df35 Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16.1.2 GlobIterForTiming | Checksum: 644b723e Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16.1 Global Iteration 0 | Checksum: 644b723e Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 152ba6993 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.311 | TNS=-3.16 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: ac1d243f Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 16 Rip-up And Reroute | Checksum: ac1d243f Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: ac1d243f Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.127 | TNS=-0.431 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.127 | TNS=-0.42 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.127 | TNS=-0.42 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1581.648 ; gain = 93.004 Phase 21 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.064 | TNS=-0.208 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 21 Post Router Timing | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1581.648 ; gain = 93.004 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 1572aeb0e Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1581.648 ; gain = 93.004 Routing Is Done. Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1583.855 ; gain = 95.211 INFO: [Common 17-83] Releasing license: Implementation 27 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:23 . Memory (MB): peak = 1583.855 ; gain = 100.207 # write_checkpoint -force $ODIR/post_route Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1583.855 ; gain = 0.000 # report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type max -sort_by slack. Startpoint Endpoint Slack ------------------------------------------------------------------- xor_xnor_inst2/xor_out_reg[5]/C vect_bias_inst2a/ones_reg[3]/D -0.064 xor_xnor_inst2/xor_out_reg[5]/C vect_bias_inst2a/ones_reg[2]/D -0.062 xor_xnor_inst2/xor_out_reg[6]/C vect_bias_inst2a/zeros_reg[3]/D -0.054 xor_xnor_inst2/xor_out_reg[2]/C vect_bias_inst2b/zeros_reg[3]/D -0.021 xor_xnor_inst2/xor_out_reg[4]/C vect_bias_inst2b/zeros_reg[2]/D -0.007 # report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type min -sort_by slack. INFO: [Timing 38-72] No paths found. No timing paths found. # report_pulse_width -significant_digits 3 -all_violators INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- | Tool Version : Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 | Date : Tue May 6 05:02:11 2014 | Host : neuromancer.lan running 64-bit Mageia 2 | Command : report_pulse_width -significant_digits 3 -all_violators | Design : top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.10 2014-03-13 ----------------------------------------------------------------------------------- Pulse Width Report place_design -post_place_opt Command: place_design -post_place_opt Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.1 Build Super Logic Region (SLR) Database Phase 1.1.1 Build Super Logic Region (SLR) Database | Checksum: 1123d189f Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.2 Add Constraints Phase 1.1.2 Add Constraints | Checksum: 18d18a17c Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.3 Build Macros Phase 1.1.3 Build Macros | Checksum: 18d18a17c Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.4 Implementation Feasibility check Phase 1.1.4 Implementation Feasibility check | Checksum: 18d18a17c Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.5 Placer Initialization Phase 1.1.5.1 Build Placer Netlist Model Phase 1.1.5.1.1 Place Init Design Phase 1.1.5.1.1.1 Build Clock Data Phase 1.1.5.1.1.1 Build Clock Data | Checksum: 21f285dd8 Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1583.855 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1.1.5.1.1 Place Init Design | Checksum: 1de93b254 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.5.1 Build Placer Netlist Model | Checksum: 1de93b254 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros Phase 1.1.5.2.1 Constrain Global/Regional Clocks Phase 1.1.5.2.1 Constrain Global/Regional Clocks | Checksum: 1de93b254 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros | Checksum: 1de93b254 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1.5 Placer Initialization | Checksum: 1de93b254 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1.1 Placer Initialization Core | Checksum: 1de93b254 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 1de93b254 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 2 Constrain Global/Regional Clocks Phase 2 Constrain Global/Regional Clocks | Checksum: 1de93b254 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1de93b254 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 3.2 Commit Small Macros & Core Logic Phase 3.2 Commit Small Macros & Core Logic | Checksum: 22df0751d Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 22df0751d Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 22df0751d Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.108. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.2 Post Placement Optimization | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.4 Placer Reporting | Checksum: 218b37457 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 2786085aa Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2786085aa Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 Ending Placer Task | Checksum: 1eef1bc76 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1583.855 ; gain = 0.000 phys_opt_design -directive AlternateDelayModeling Command: phys_opt_design -directive AlternateDelayModeling Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateDelayModeling INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1 Physical Synthesis Initialization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.138 | TNS=-1.020 | Phase 2 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 2 Fanout Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 3 Placement Based Optimization INFO: [Physopt 32-540] No nets found for placement-based optimization. Phase 3 Placement Based Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 4 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 4 Rewire | Checksum: 2148f7223 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 5 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 5 Critical Cell Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 6 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 6 DSP Register Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 7 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 7 BRAM Register Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 8 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 8 Shift Register Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 9 Critical Pin Optimization INFO: [Physopt 32-607] No candidate nets found for critical-pin optimization. Phase 9 Critical Pin Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 10 Very High Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 10 Very High Fanout Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 11 BRAM Enable Optimization Phase 11 BRAM Enable Optimization | Checksum: 2148f7223 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1583.855 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.138 | TNS=-1.020 | Ending Physical Synthesis Task | Checksum: 2148f7223 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1583.855 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d6ba0bac Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1583.855 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d6ba0bac Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1583.855 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 14a313624 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0884| TNS=-0.397 | WHS=-0.133 | THS=-3.17 | Phase 2 Router Initialization | Checksum: 14a313624 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 991b9dd8 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 69 Number of Nodes with overlaps = 49 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 7 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y17/IMUX4 Overlapping nets: 2 xor_xnor_inst2/xor_out[7] xor_xnor_inst2/xor_out[3] 2. INT_L_X28Y15/IMUX_L44 Overlapping nets: 2 xor_xnor_inst2/xor_out[6] xor_xnor_inst2/xnor_out[7] 3. INT_R_X29Y17/IMUX12 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[6] 4. INT_L_X28Y17/IMUX_L43 Overlapping nets: 2 vect_bias_inst2b/vect_bias_net_1 vect_bias_inst2b/vect_bias_net_2 5. INT_L_X28Y18/IMUX_L35 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xnor_out[7] 6. INT_L_X28Y15/IMUX_L38 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xnor_out[3] 7. INT_R_X29Y17/IMUX1 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[5] Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 1c773267c Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.343 | TNS=-2.07 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 19472bae Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 19472bae Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4.1.2 GlobIterForTiming | Checksum: 1648c9623 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4.1 Global Iteration 0 | Checksum: 1648c9623 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 44 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 152f26259 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.461 | TNS=-2.86 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1c773267c Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 4 Rip-up And Reroute | Checksum: 1c773267c Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 1c773267c Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.19 | TNS=-0.471 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.178 | TNS=-0.487 | WHS=0.105 | THS=0 | Phase 7 Post Hold Fix | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.178 | TNS=-0.487 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0982545 % Global Horizontal Routing Utilization = 0.064568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions. South Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions. East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 9 Route finalize | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1589.707 ; gain = 5.852 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 142b1ded6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1590.707 ; gain = 6.852 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 19f7e3054 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1590.707 ; gain = 6.852 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1590.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.079. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 19f7e3054 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.707 ; gain = 6.852 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: 14c421c9c Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.707 ; gain = 6.852 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: 14c421c9c Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.711 ; gain = 6.855 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 12ae1140a Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.16 | TNS=-1.35 | WHS=-0.133 | THS=-2.93 | Phase 14 Router Initialization | Checksum: 12ae1140a Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 8888cffb Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 44 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 9 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y54/IMUX36 Overlapping nets: 2 din1_d[4] din1_d[6] 2. INT_L_X28Y16/IMUX_L35 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xnor_out[7] 3. INT_R_X29Y17/IMUX38 Overlapping nets: 2 xor_xnor_inst2/xor_out[6] xor_xnor_inst2/xor_out[3] 4. INT_L_X28Y16/IMUX_L22 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xnor_out[5] 5. INT_R_X29Y54/IMUX7 Overlapping nets: 2 din1_d[2] din1_d[5] 6. INT_R_X29Y53/IMUX47 Overlapping nets: 2 din1_d[4] din1_d[3] 7. INT_R_X29Y17/IMUX15 Overlapping nets: 2 xor_xnor_inst2/xor_out[3] xor_xnor_inst2/xor_out[5] 8. INT_R_X29Y17/IMUX1 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[7] 9. INT_L_X28Y15/NL1BEG2 Overlapping nets: 2 vect_bias_inst2b/vect_bias_net_1 xor_xnor_inst2/xnor_out[7] Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: b53fbd5b Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.233 | TNS=-2.01 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 14ccb75df Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 14ccb75df Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16.1.2 GlobIterForTiming | Checksum: ec3474f2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16.1 Global Iteration 0 | Checksum: ec3474f2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: a5b404ef Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.322 | TNS=-2.11 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: adbd0eb8 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 16 Rip-up And Reroute | Checksum: adbd0eb8 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: adbd0eb8 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0804| TNS=-0.256 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0804| TNS=-0.234 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0804| TNS=-0.234 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0978322 % Global Horizontal Routing Utilization = 0.0643382 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. Phase 21 Route finalize | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 7a2288ac Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 77f12e1d Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.079 | TNS=-0.225 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: 77f12e1d Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 77f12e1d Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 Routing Is Done. Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.711 ; gain = 6.855 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.711 ; gain = 6.855 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1a70d9968 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1590.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1a70d9968 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1590.711 ; gain = 0.000 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 54a5249d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0787| TNS=-0.225 | WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 54a5249d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.234 | TNS=-2.26 | WHS=-0.133 | THS=-2.91 | Phase 2 Router Initialization | Checksum: 54a5249d Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 54a5249d Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 54a5249d Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.233 | TNS=-2.24 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 1a80d016d Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 1a80d016d Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.1.2 GlobIterForTiming | Checksum: bc9935af Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.1 Global Iteration 0 | Checksum: bc9935af Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 50 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_L_X28Y16/IMUX_L28 Overlapping nets: 2 xor_xnor_inst2/xnor_out[5] xor_xnor_inst2/xor_out[6] Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: b5f668db Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.208 | TNS=-1.88 | WHS=N/A | THS=N/A | Phase 4.2.2 GlobIterForTiming Phase 4.2.2.1 Update Timing Phase 4.2.2.1 Update Timing | Checksum: d2cd37c1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.2.2.2 Fast Budgeting Phase 4.2.2.2 Fast Budgeting | Checksum: d2cd37c1 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.2.2 GlobIterForTiming | Checksum: 403b0916 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.2 Global Iteration 1 | Checksum: 403b0916 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y16/IMUX12 Overlapping nets: 2 xor_xnor_inst2/xor_out[6] xor_xnor_inst2/xor_out[3] 2. INT_R_X29Y54/IMUX5 Overlapping nets: 2 din1_d[7] din1_d[2] 3. INT_L_X28Y54/EL1BEG2 Overlapping nets: 2 din1_d[7] din1_d[4] Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y54/IMUX3 Overlapping nets: 2 din1_d[2] din1_d[5] Number of Nodes with overlaps = 0 Phase 4.3.1 Update Timing Phase 4.3.1 Update Timing | Checksum: 17e4a2477 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.26 | TNS=-2.08 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: b5f668db Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 4 Rip-up And Reroute | Checksum: b5f668db Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: b5f668db Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0558| TNS=-0.145 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0558| TNS=-0.123 | WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0558| TNS=-0.123 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0983953 % Global Horizontal Routing Utilization = 0.0675551 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. Phase 9 Route finalize | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1594.707 ; gain = 3.996 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 13baf28ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1596.707 ; gain = 5.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 1a19a3220 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1596.707 ; gain = 5.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1596.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.050. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 1a19a3220 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1596.707 ; gain = 5.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: a43ea2c5 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1596.707 ; gain = 5.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: a43ea2c5 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1596.711 ; gain = 6.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: ce47b7a0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.183 | TNS=-1.06 | WHS=-0.133 | THS=-2.96 | Phase 14 Router Initialization | Checksum: ce47b7a0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 14ad83ff7 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 6 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y54/IMUX4 Overlapping nets: 2 din1_d[7] din1_d[3] 2. INT_L_X28Y18/IMUX_L18 Overlapping nets: 2 xor_xnor_inst2/xor_out[6] xor_xnor_inst2/xnor_out[7] 3. INT_R_X29Y17/IMUX11 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[6] 4. INT_L_X28Y15/IMUX_L47 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[6] 5. INT_L_X28Y18/IMUX_L31 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xnor_out[7] 6. INT_R_X29Y16/IMUX17 Overlapping nets: 2 xor_xnor_inst2/xor_out[7] xor_xnor_inst2/xor_out[5] Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 126583d1b Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.191 | TNS=-1.54 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 12e3af482 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 12e3af482 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16.1.2 GlobIterForTiming | Checksum: 5adbb081 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16.1 Global Iteration 0 | Checksum: 5adbb081 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y17/IMUX1 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[3] 2. INT_R_X29Y16/IMUX1 Overlapping nets: 2 xor_xnor_inst2/xor_out[7] xor_xnor_inst2/xor_out[5] 3. INT_R_X29Y17/SL1BEG3 Overlapping nets: 2 xor_xnor_inst2/xor_out[5] vect_bias_inst2a/vect_bias__2_net_2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 132171459 Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.323 | TNS=-2.43 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: 1acf3bd1f Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 16 Rip-up And Reroute | Checksum: 1acf3bd1f Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: 1acf3bd1f Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0384| TNS=-0.0384| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 12d511552 Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 12d511552 Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0254| TNS=-0.0254| WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0254| TNS=-0.0254| WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0958615 % Global Horizontal Routing Utilization = 0.0638787 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. Phase 21 Route finalize | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1597.707 ; gain = 6.996 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 12d511552 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: d1f1e6e1 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.022 | TNS=-0.022 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: d1f1e6e1 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: d1f1e6e1 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 Routing Is Done. Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 INFO: [Common 17-83] Releasing license: Implementation 31 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1599.707 ; gain = 8.996 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: acd6d867 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1599.707 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: acd6d867 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1599.711 ; gain = 0.004 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 6ebc9dda Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0219| TNS=-0.0219| WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 6ebc9dda Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.179 | TNS=-1.51 | WHS=-0.133 | THS=-2.96 | Phase 2 Router Initialization | Checksum: 6ebc9dda Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6ebc9dda Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 6ebc9dda Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.178 | TNS=-1.49 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 7aa00d4b Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 7aa00d4b Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4.1.2 GlobIterForTiming | Checksum: 2b929904 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4.1 Global Iteration 0 | Checksum: 2b929904 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y16/IMUX18 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[3] Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 1609fbe21 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.305 | TNS=-2.16 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 4 Rip-up And Reroute | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0238| TNS=-0.0238| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0238| TNS=-0.0238| WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0238| TNS=-0.0238| WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0958615 % Global Horizontal Routing Utilization = 0.0638787 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. South Dir 1x1 Area, Max Cong = 29.7297%, No Congested Regions. East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. Phase 9 Route finalize | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1601.707 ; gain = 2.000 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1603.707 ; gain = 4.000 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: db049780 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1603.707 ; gain = 4.000 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1603.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.050. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: db049780 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.707 ; gain = 4.000 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: e12f89d0 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.707 ; gain = 4.000 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: e12f89d0 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.711 ; gain = 4.004 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: d7a4c738 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.179 | TNS=-1.16 | WHS=-0.133 | THS=-2.96 | Phase 14 Router Initialization | Checksum: d7a4c738 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 14d43c075 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 9e1ba3a5 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.243 | TNS=-1.82 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: fb3bb0fa Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: fb3bb0fa Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16.1.2 GlobIterForTiming | Checksum: 104ab6599 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16.1 Global Iteration 0 | Checksum: 104ab6599 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 33 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 1b3113486 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.377 | TNS=-2.37 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: 9e1ba3a5 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 16 Rip-up And Reroute | Checksum: 9e1ba3a5 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: 9e1ba3a5 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0904| TNS=-0.21 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0904| TNS=-0.21 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0904| TNS=-0.21 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Phase 21 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.022 | TNS=-0.022 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 21 Post Router Timing | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 638c4632 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 Routing Is Done. Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1603.711 ; gain = 4.004 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1603.711 ; gain = 4.004 report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type max -sort_by slack. Startpoint Endpoint Slack ------------------------------------------------------------------- xor_xnor_inst2/xor_out_reg[6]/C vect_bias_inst2b/ones_reg[2]/D -0.022 report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type min -sort_by slack. INFO: [Timing 38-72] No paths found. No timing paths found. report_pulse_width -significant_digits 3 -all_violators INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- | Tool Version : Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 | Date : Tue May 6 05:04:11 2014 | Host : neuromancer.lan running 64-bit Mageia 2 | Command : report_pulse_width -significant_digits 3 -all_violators | Design : top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.10 2014-03-13 ----------------------------------------------------------------------------------- Pulse Width Report place_design -post_place_opt Command: place_design -post_place_opt Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.1 Build Super Logic Region (SLR) Database Phase 1.1.1 Build Super Logic Region (SLR) Database | Checksum: 75a0500b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.2 Add Constraints Phase 1.1.2 Add Constraints | Checksum: f07bd8e8 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.3 Build Macros Phase 1.1.3 Build Macros | Checksum: f07bd8e8 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.4 Implementation Feasibility check Phase 1.1.4 Implementation Feasibility check | Checksum: f07bd8e8 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.5 Placer Initialization Phase 1.1.5.1 Build Placer Netlist Model Phase 1.1.5.1.1 Place Init Design Phase 1.1.5.1.1.1 Build Clock Data Phase 1.1.5.1.1.1 Build Clock Data | Checksum: 18c20a895 Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1603.711 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1.1.5.1.1 Place Init Design | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.5.1 Build Placer Netlist Model | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros Phase 1.1.5.2.1 Constrain Global/Regional Clocks Phase 1.1.5.2.1 Constrain Global/Regional Clocks | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.5.2 Constrain Clocks/Macros | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1.5 Placer Initialization | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1.1 Placer Initialization Core | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 2 Constrain Global/Regional Clocks Phase 2 Constrain Global/Regional Clocks | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1494c3c11 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 3.2 Commit Small Macros & Core Logic Phase 3.2 Commit Small Macros & Core Logic | Checksum: 25e6e4800 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 25e6e4800 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 25e6e4800 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.2.1.2 updateTiming after Restore Best Placement Phase 4.2.1.2 updateTiming after Restore Best Placement | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.058. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.2 Post Placement Optimization | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.4 Placer Reporting | Checksum: 1d1c9f60e Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 231770761 Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 231770761 Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 Ending Placer Task | Checksum: 1784c8b66 Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1603.711 ; gain = 0.000 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: fdb6f610 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1603.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: fdb6f610 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1603.711 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 6cdd5ff6 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.109 | TNS=-0.781 | WHS=-0.133 | THS=-3.23 | Phase 2 Router Initialization | Checksum: 6cdd5ff6 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: e57ba352 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 50 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_L_X28Y17/IMUX_L2 Overlapping nets: 2 xor_xnor_inst2/xnor_out[3] xor_xnor_inst2/xor_out[4] Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 18ceb2466 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.367 | TNS=-2.34 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: e7f8d536 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: e7f8d536 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4.1.2 GlobIterForTiming | Checksum: 1835e4251 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4.1 Global Iteration 0 | Checksum: 1835e4251 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: aa4adef3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.415 | TNS=-2.48 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: d8b30718 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 4 Rip-up And Reroute | Checksum: d8b30718 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: d8b30718 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.214 | TNS=-0.56 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.192 | TNS=-0.429 | WHS=0.105 | THS=0 | Phase 7 Post Hold Fix | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.192 | TNS=-0.429 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0957207 % Global Horizontal Routing Utilization = 0.0664062 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. South Dir 1x1 Area, Max Cong = 28.8288%, No Congested Regions. East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. Phase 9 Route finalize | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 7e50e3e0 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 11666efeb Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1607.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.054. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 11666efeb Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: c92d3fef Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1607.707 ; gain = 3.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: c92d3fef Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1607.711 ; gain = 4.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 19c18206c Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.185 | TNS=-1.37 | WHS=-0.133 | THS=-3.48 | Phase 14 Router Initialization | Checksum: 19c18206c Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: e2196a0b Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 49 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 6 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: df61a3d9 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.21 | TNS=-1.92 | WHS=N/A | THS=N/A | Phase 16.1 Global Iteration 0 | Checksum: df61a3d9 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 185d6c1a4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.32 | TNS=-2.89 | WHS=N/A | THS=N/A | Phase 16.2.2 GlobIterForTiming Phase 16.2.2.1 Update Timing Phase 16.2.2.1 Update Timing | Checksum: 1255527eb Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16.2.2.2 Fast Budgeting Phase 16.2.2.2 Fast Budgeting | Checksum: 1255527eb Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16.2.2 GlobIterForTiming | Checksum: 70bbc900 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16.2 Global Iteration 1 | Checksum: 70bbc900 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16.3 Global Iteration 2 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 Phase 16.3.1 Update Timing Phase 16.3.1 Update Timing | Checksum: 1228685f0 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.381 | TNS=-3.62 | WHS=N/A | THS=N/A | Phase 16.3 Global Iteration 2 | Checksum: 185d6c1a4 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 16 Rip-up And Reroute | Checksum: 185d6c1a4 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: 185d6c1a4 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.167 | TNS=-0.72 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.154 | TNS=-0.64 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.154 | TNS=-0.64 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: c37d5e22 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0964245 % Global Horizontal Routing Utilization = 0.0631893 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions. East Dir 1x1 Area, Max Cong = 25%, No Congested Regions. West Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions. Phase 21 Route finalize | Checksum: c37d5e22 Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: c37d5e22 Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: c81aeb2b Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.153 | TNS=-0.626 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: c81aeb2b Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: c81aeb2b Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 Routing Is Done. Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1607.711 ; gain = 4.000 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1607.711 ; gain = 4.000 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 66764785 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1607.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 66764785 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1607.711 ; gain = 0.000 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: f4a75821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.153 | TNS=-0.626 | WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: f4a75821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.309 | TNS=-2.65 | WHS=-0.133 | THS=-3.47 | Phase 2 Router Initialization | Checksum: f4a75821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f4a75821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: f4a75821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.307 | TNS=-2.63 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 1107cb915 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 1107cb915 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.1.2 GlobIterForTiming | Checksum: 1b9bc7997 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.1 Global Iteration 0 | Checksum: 1b9bc7997 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 59 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 1413b2e29 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.289 | TNS=-2.42 | WHS=N/A | THS=N/A | Phase 4.2.2 GlobIterForTiming Phase 4.2.2.1 Update Timing Phase 4.2.2.1 Update Timing | Checksum: 1913906c9 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.2.2.2 Fast Budgeting Phase 4.2.2.2 Fast Budgeting | Checksum: 1913906c9 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.2.2 GlobIterForTiming | Checksum: 1c9a5e482 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.2 Global Iteration 1 | Checksum: 1c9a5e482 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.3.1 Update Timing Phase 4.3.1 Update Timing | Checksum: 19c578c0e Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.349 | TNS=-2.62 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1413b2e29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 4 Rip-up And Reroute | Checksum: 1413b2e29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 1413b2e29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.137 | TNS=-0.415 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.137 | TNS=-0.398 | WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.137 | TNS=-0.398 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0962838 % Global Horizontal Routing Utilization = 0.0668658 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions. East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. Phase 9 Route finalize | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 6f43a811 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: c65d8770 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1611.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.082. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: c65d8770 Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: 174f0deb3 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1611.707 ; gain = 3.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: 174f0deb3 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1611.711 ; gain = 4.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 17031ee44 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.216 | TNS=-1.29 | WHS=-0.133 | THS=-3.36 | Phase 14 Router Initialization | Checksum: 17031ee44 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 135eb2d50 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 952011d4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.351 | TNS=-1.92 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 12bba44f7 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 12bba44f7 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.1.2 GlobIterForTiming | Checksum: 7003ba2e Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.1 Global Iteration 0 | Checksum: 7003ba2e Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 44 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 5f98ddc4 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.342 | TNS=-2.03 | WHS=N/A | THS=N/A | Phase 16.2.2 GlobIterForTiming Phase 16.2.2.1 Update Timing Phase 16.2.2.1 Update Timing | Checksum: 12348b82a Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.2.2.2 Fast Budgeting Phase 16.2.2.2 Fast Budgeting | Checksum: 12348b82a Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.2.2 GlobIterForTiming | Checksum: 95391a0d Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.2 Global Iteration 1 | Checksum: 95391a0d Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.3 Global Iteration 2 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_L_X28Y17/IMUX_L18 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xnor_out[7] 2. INT_R_X29Y18/IMUX47 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[7] Number of Nodes with overlaps = 0 Phase 16.3.1 Update Timing Phase 16.3.1 Update Timing | Checksum: 142f03b31 Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.309 | TNS=-1.87 | WHS=N/A | THS=N/A | Phase 16.3.2 GlobIterForTiming Phase 16.3.2.1 Update Timing Phase 16.3.2.1 Update Timing | Checksum: 1104ac9b7 Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.3.2.2 Fast Budgeting Phase 16.3.2.2 Fast Budgeting | Checksum: 1104ac9b7 Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.3.2 GlobIterForTiming | Checksum: 197cda69f Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.3 Global Iteration 2 | Checksum: 197cda69f Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.4 Global Iteration 3 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 16.4.1 Update Timing Phase 16.4.1 Update Timing | Checksum: e12dfb09 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.218 | TNS=-2.19 | WHS=N/A | THS=N/A | Phase 16.4.2 GlobIterForTiming Phase 16.4.2.1 Update Timing Phase 16.4.2.1 Update Timing | Checksum: 1246f7c79 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.4.2.2 Fast Budgeting Phase 16.4.2.2 Fast Budgeting | Checksum: 1246f7c79 Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.4.2 GlobIterForTiming | Checksum: eef17dea Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.4 Global Iteration 3 | Checksum: eef17dea Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16.5 Global Iteration 4 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 INFO: [Route 35-325] The following overlapped nodes exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y17/IMUX44 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[4] 2. INT_R_X29Y17/IMUX8 Overlapping nets: 2 xor_xnor_inst2/xor_out[4] xor_xnor_inst2/xor_out[3] 3. INT_R_X29Y54/IMUX41 Overlapping nets: 2 din1_d[2] din1_d[5] 4. INT_R_X29Y17/IMUX1 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[5] Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 16.5.1 Update Timing Phase 16.5.1 Update Timing | Checksum: 5f97c53e Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.22 | TNS=-1.28 | WHS=N/A | THS=N/A | Phase 16.5 Global Iteration 4 | Checksum: e12dfb09 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 16 Rip-up And Reroute | Checksum: e12dfb09 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: e12dfb09 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0654| TNS=-0.273 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0634| TNS=-0.199 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0634| TNS=-0.199 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0967061 % Global Horizontal Routing Utilization = 0.0693934 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. Phase 21 Route finalize | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1611.711 ; gain = 4.000 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 11bc66191 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1613.707 ; gain = 5.996 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: eef4f39d Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1613.707 ; gain = 5.996 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.061 | TNS=-0.194 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: eef4f39d Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1613.707 ; gain = 5.996 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: eef4f39d Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1613.707 ; gain = 5.996 Routing Is Done. Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1613.707 ; gain = 5.996 INFO: [Common 17-83] Releasing license: Implementation 31 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1613.707 ; gain = 5.996 place_design -post_place_opt Command: place_design -post_place_opt Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 1.1.1 Build Super Logic Region (SLR) Database Phase 1.1.1 Build Super Logic Region (SLR) Database | Checksum: c3056d17 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.2 Add Constraints Phase 1.1.2 Add Constraints | Checksum: 13de0f5f4 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.3 Build Macros Phase 1.1.3 Build Macros | Checksum: 13de0f5f4 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.4 Implementation Feasibility check Phase 1.1.4 Implementation Feasibility check | Checksum: 13de0f5f4 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.5 Placer Initialization Phase 1.1.5.1 Build Placer Netlist Model Phase 1.1.5.1.1 Place Init Design Phase 1.1.5.1.1.1 Build Clock Data Phase 1.1.5.1.1.1 Build Clock Data | Checksum: 1fdfae5f5 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1613.711 ; gain = 0.004 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1.1.5.1.1 Place Init Design | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.5.1 Build Placer Netlist Model | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.5.2 Constrain Clocks/Macros Phase 1.1.5.2.1 Constrain Global/Regional Clocks Phase 1.1.5.2.1 Constrain Global/Regional Clocks | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.5.2 Constrain Clocks/Macros | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1.5 Placer Initialization | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1.1 Placer Initialization Core | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 1 Placer Initialization | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 2 Constrain Global/Regional Clocks Phase 2 Constrain Global/Regional Clocks | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21ce4b562 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 3.2 Commit Small Macros & Core Logic Phase 3.2 Commit Small Macros & Core Logic | Checksum: 1d8e97662 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 3 Detail Placement | Checksum: 1d8e97662 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 1d8e97662 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1.1 Restore Best Placement Phase 4.2.1.1 Restore Best Placement | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.095. For the most accurate timing information please run report_timing. Phase 4.2.1 Post Placement Timing Optimization | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.2 Post Placement Optimization | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.4 Placer Reporting Phase 4.4.1 Restore STA Phase 4.4.1 Restore STA | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.4 Placer Reporting | Checksum: fcf1d3a2 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 15c9ee4f5 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15c9ee4f5 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 Ending Placer Task | Checksum: 15440c1cc Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 INFO: [Common 17-83] Releasing license: Implementation 7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1613.711 ; gain = 0.004 phys_opt_design -directive Explore Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. Phase 1 Physical Synthesis Initialization | Checksum: 179de7779 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1613.711 ; gain = 0.000 INFO: [Physopt 32-245] Routed nets are present in the design. phys_opt_design will optimize unrouted part of the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1613.711 ; gain = 0.000 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.083 | TNS=-0.235 | Phase 2 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 2 Fanout Optimization | Checksum: 179de7779 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 1 candidate net for placement-based optimization. INFO: [Physopt 32-663] Processed net din1_d[2]. Re-placed instance din1_d_reg[2] INFO: [Physopt 32-661] Optimized 1 net. Re-placed 1 instance. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.056 | TNS=-0.134 | Phase 3 Placement Based Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 4 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 4 Rewire | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 5 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 5 Critical Cell Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 6 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 6 Fanout Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 7 Placement Based Optimization INFO: [Physopt 32-660] Identified 1 candidate net for placement-based optimization. INFO: [Physopt 32-662] Processed net din1_d[2]. Did not re-place instance din1_d_reg[2] INFO: [Physopt 32-661] Optimized 0 nets. Re-placed 0 instances. Phase 7 Placement Based Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 8 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 8 Rewire | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 9 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 9 Critical Cell Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 10 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 10 Fanout Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.78 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 11 Placement Based Optimization INFO: [Physopt 32-660] Identified 1 candidate net for placement-based optimization. INFO: [Physopt 32-662] Processed net din1_d[2]. Did not re-place instance din1_d_reg[2] INFO: [Physopt 32-661] Optimized 0 nets. Re-placed 0 instances. Phase 11 Placement Based Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 12 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring (Signal Push) optimization. Phase 12 Rewire | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 13 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. Phase 13 Critical Cell Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 14 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 14 DSP Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 15 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 15 BRAM Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 16 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 16 Shift Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 17 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. Phase 17 DSP Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 18 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design Phase 18 BRAM Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 19 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design Phase 19 Shift Register Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 20 Critical Pin Optimization INFO: [Physopt 32-607] No candidate nets found for critical-pin optimization. Phase 20 Critical Pin Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 21 Very High Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. Phase 21 Very High Fanout Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 22 BRAM Enable Optimization Phase 22 BRAM Enable Optimization | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1613.711 ; gain = 0.000 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.056 | TNS=-0.134 | Ending Physical Synthesis Task | Checksum: 172eeb9e6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1613.711 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 16cb3749c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1613.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 16cb3749c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1613.711 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: b413c225 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.16 | TNS=-0.727 | WHS=-0.133 | THS=-3.17 | Phase 2 Router Initialization | Checksum: b413c225 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 16632a838 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 53 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 101ac1eb9 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.269 | TNS=-2.1 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 1170fa682 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 1170fa682 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4.1.2 GlobIterForTiming | Checksum: 155ce9a6d Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4.1 Global Iteration 0 | Checksum: 155ce9a6d Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 594da026 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.32 | TNS=-2.4 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 335d509c Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 4 Rip-up And Reroute | Checksum: 335d509c Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 335d509c Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.116 | TNS=-0.407 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.116 | TNS=-0.405 | WHS=0.105 | THS=0 | Phase 7 Post Hold Fix | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.116 | TNS=-0.405 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0995214 % Global Horizontal Routing Utilization = 0.0664062 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 9 Route finalize | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1616.707 ; gain = 2.996 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: d7f16675 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1618.707 ; gain = 4.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 1fa17011 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1618.707 ; gain = 4.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1618.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.097. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 1fa17011 Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.707 ; gain = 4.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: bc1d31ac Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.707 ; gain = 4.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: bc1d31ac Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.711 ; gain = 5.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 1539fd100 Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.215 | TNS=-1.12 | WHS=-0.133 | THS=-3.61 | Phase 14 Router Initialization | Checksum: 1539fd100 Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: f0aadb0e Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 74e0f771 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.239 | TNS=-1.46 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: f047fcfd Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: f047fcfd Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16.1.2 GlobIterForTiming | Checksum: 7d9d2682 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16.1 Global Iteration 0 | Checksum: 7d9d2682 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 18a4de39a Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.345 | TNS=-2.25 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: 74e0f771 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 16 Rip-up And Reroute | Checksum: 74e0f771 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: 74e0f771 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0864| TNS=-0.146 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0624| TNS=-0.106 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0624| TNS=-0.106 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0983953 % Global Horizontal Routing Utilization = 0.0654871 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. South Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions. East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 21 Route finalize | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 102d888a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: f2f6d383 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.061 | TNS=-0.102 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: f2f6d383 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: f2f6d383 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 Routing Is Done. Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 INFO: [Common 17-83] Releasing license: Implementation 24 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 1618.711 ; gain = 5.000 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 11a48b78c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1618.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 11a48b78c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1618.711 ; gain = 0.000 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 10552d60f Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0606| TNS=-0.102 | WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 10552d60f Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.216 | TNS=-1.37 | WHS=-0.133 | THS=-3.61 | Phase 2 Router Initialization | Checksum: 10552d60f Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10552d60f Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 10552d60f Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.215 | TNS=-1.35 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 1627f3603 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 1627f3603 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4.1.2 GlobIterForTiming | Checksum: aff3ee89 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4.1 Global Iteration 0 | Checksum: aff3ee89 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 62 Number of Nodes with overlaps = 57 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 10ee2b65d Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.348 | TNS=-2.56 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: ee085247 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 4 Rip-up And Reroute | Checksum: ee085247 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: ee085247 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0628| TNS=-0.107 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0628| TNS=-0.104 | WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0628| TNS=-0.104 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0983953 % Global Horizontal Routing Utilization = 0.0652574 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. South Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions. East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 9 Route finalize | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1620.707 ; gain = 1.996 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.707 ; gain = 3.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 1d1b4a71e Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.707 ; gain = 3.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1622.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.010. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 1d1b4a71e Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.707 ; gain = 3.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: eda8f00a Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.707 ; gain = 3.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: eda8f00a Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.711 ; gain = 4.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: 18e9c7dbc Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.128 | TNS=-0.553 | WHS=-0.133 | THS=-3.65 | Phase 14 Router Initialization | Checksum: 18e9c7dbc Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: 104b40ef0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 70 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 13a0415e8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.224 | TNS=-1.01 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 5ce55e45 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 5ce55e45 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16.1.2 GlobIterForTiming | Checksum: 7601f4af Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16.1 Global Iteration 0 | Checksum: 7601f4af Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 9df107ac Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.276 | TNS=-2.68 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: e0059c39 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 16 Rip-up And Reroute | Checksum: e0059c39 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: e0059c39 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0714| TNS=-0.129 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0584| TNS=-0.103 | WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0584| TNS=-0.103 | WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0967061 % Global Horizontal Routing Utilization = 0.0636489 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. Phase 21 Route finalize | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 168f8b579 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 174bc4323 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.056 | TNS=-0.099 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: 174bc4323 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 174bc4323 Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 Routing Is Done. Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1622.711 ; gain = 4.000 INFO: [Common 17-83] Releasing license: Implementation 25 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1622.711 ; gain = 4.000 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 4ed9230c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 4ed9230c Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: d1b912b1 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0564| TNS=-0.099 | WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: d1b912b1 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.212 | TNS=-0.971 | WHS=-0.133 | THS=-3.63 | Phase 2 Router Initialization | Checksum: d1b912b1 Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: d1b912b1 Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: d1b912b1 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.211 | TNS=-0.966 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 18662f7fe Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 18662f7fe Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4.1.2 GlobIterForTiming | Checksum: f8f0df77 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4.1 Global Iteration 0 | Checksum: f8f0df77 Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 55 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 148abdd8f Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.305 | TNS=-1.98 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 4 Rip-up And Reroute | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0588| TNS=-0.104 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0588| TNS=-0.104 | WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1622.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0588| TNS=-0.104 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0967061 % Global Horizontal Routing Utilization = 0.0636489 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. Phase 9 Route finalize | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1622.711 ; gain = 0.000 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.707 ; gain = 1.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 6e065331 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.707 ; gain = 1.996 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1624.707 ; gain = 0.000 WARNING: [Place 30-41] Flop utilization in 'PBLOCK: pblock_inst2a' is very high, this is forcing placer to place 8 flops per slice which will lower the chances of successful completion. INFO: [Place 30-746] Post Placement Timing Summary WNS=0.011. For the most accurate timing information please run report_timing. Phase 12 Incr Placement Change | Checksum: 6e065331 Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1624.707 ; gain = 1.996 Phase 13 Build RT Design Phase 13 Build RT Design | Checksum: a14899ef Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1624.707 ; gain = 1.996 Phase 14 Router Initialization Phase 14.1 Create Timer Phase 14.1 Create Timer | Checksum: a14899ef Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1624.711 ; gain = 2.000 Number of Nodes with overlaps = 0 Phase 14.2 Update Timing Phase 14.2 Update Timing | Checksum: ad6ad873 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.126 | TNS=-0.56 | WHS=-0.133 | THS=-3.68 | Phase 14 Router Initialization | Checksum: ad6ad873 Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 15 Initial Routing Phase 15 Initial Routing | Checksum: a21f783f Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16 Rip-up And Reroute Phase 16.1 Global Iteration 0 Number of Nodes with overlaps = 49 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.175 | TNS=-1.3 | WHS=N/A | THS=N/A | Phase 16.1.2 GlobIterForTiming Phase 16.1.2.1 Update Timing Phase 16.1.2.1 Update Timing | Checksum: 856a0412 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16.1.2.2 Fast Budgeting Phase 16.1.2.2 Fast Budgeting | Checksum: 856a0412 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16.1.2 GlobIterForTiming | Checksum: 1184e4124 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16.1 Global Iteration 0 | Checksum: 1184e4124 Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16.2 Global Iteration 1 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_L_X28Y17/IMUX_L17 Overlapping nets: 2 xor_xnor_inst2/xnor_out[3] xor_xnor_inst2/xnor_out[5] Number of Nodes with overlaps = 0 Phase 16.2.1 Update Timing Phase 16.2.1 Update Timing | Checksum: 3c911907 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.259 | TNS=-1.39 | WHS=N/A | THS=N/A | Phase 16.2 Global Iteration 1 | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 16 Rip-up And Reroute | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 17 Delay CleanUp Phase 17.1 Update Timing Phase 17.1 Update Timing | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0224| TNS=-0.0224| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 17 Delay CleanUp | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 18 Clock Skew Optimization Phase 18 Clock Skew Optimization | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 19 Post Hold Fix Phase 19.1 Update Timing Phase 19.1 Update Timing | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0224| TNS=-0.0224| WHS=0.105 | THS=0 | Phase 19 Post Hold Fix | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0224| TNS=-0.0224| WHS=N/A | THS=N/A | Phase 20 Timing Verification | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.100648 % Global Horizontal Routing Utilization = 0.0680147 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. South Dir 1x1 Area, Max Cong = 20.7207%, No Congested Regions. East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 21 Route finalize | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 1aa0d0f31 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 167682795 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 Phase 24 Post Router Timing INFO: [Route 35-62] Timer settings changed to match sign-off timing analysis. Setup and Hold analysis on slow, fast Corners with nearest common node skew is enabled. INFO: [Route 35-20] Post Routing Timing Summary | WNS=-0.022 | TNS=-0.022 | WHS=0.122 | THS=0.000 | CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths. INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS. Phase 24 Post Router Timing | Checksum: 167682795 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 167682795 Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 Routing Is Done. Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1624.711 ; gain = 2.000 route_design -directive Explore Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Starting Route Task Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 549b7108 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 549b7108 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 2.2 Update Timing Phase 2.2 Update Timing | Checksum: 12b839464 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0217| TNS=-0.0217| WHS=0.122 | THS=0 | Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 12b839464 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.176 | TNS=-1.31 | WHS=-0.133 | THS=-3.68 | Phase 2 Router Initialization | Checksum: 12b839464 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12b839464 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 12b839464 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.175 | TNS=-1.3 | WHS=N/A | THS=N/A | Phase 4.1.2 GlobIterForTiming Phase 4.1.2.1 Update Timing Phase 4.1.2.1 Update Timing | Checksum: 17fa6a12b Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.1.2.2 Fast Budgeting Phase 4.1.2.2 Fast Budgeting | Checksum: 17fa6a12b Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.1.2 GlobIterForTiming | Checksum: 2990da3e Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.1 Global Iteration 0 | Checksum: 2990da3e Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 47 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. Resolution: Check for routing resource conflicts on the identified nets or significant localized congestion using the Route Congestion Metrics in the Device View. 1. INT_R_X29Y16/IMUX27 Overlapping nets: 2 xor_xnor_inst2/xor_out[2] xor_xnor_inst2/xor_out[5] Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 17e8efbf7 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.165 | TNS=-1.16 | WHS=N/A | THS=N/A | Phase 4.2.2 GlobIterForTiming Phase 4.2.2.1 Update Timing Phase 4.2.2.1 Update Timing | Checksum: 1a2ddd585 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.2.2.2 Fast Budgeting Phase 4.2.2.2 Fast Budgeting | Checksum: 1a2ddd585 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.2.2 GlobIterForTiming | Checksum: 11883f850 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.2 Global Iteration 1 | Checksum: 11883f850 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 Phase 4.3.1 Update Timing Phase 4.3.1 Update Timing | Checksum: ed671f67 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.288 | TNS=-1.43 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: bda960cd Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 4 Rip-up And Reroute | Checksum: bda960cd Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: bda960cd Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.0128| TNS=-0.0243| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5 Delay CleanUp | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 6 Clock Skew Optimization Phase 6 Clock Skew Optimization | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 7 Post Hold Fix Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.0112 | TNS=0 | WHS=0.12 | THS=0 | Phase 7 Post Hold Fix | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1624.711 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.0112 | TNS=0 | WHS=N/A | THS=N/A | Phase 8 Timing Verification | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.101914 % Global Horizontal Routing Utilization = 0.0735294 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Route finalize | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1624.711 ; gain = 0.000 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: e5fc9492 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 15e28a24d Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 Phase 12 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.014 | TNS=0.000 | WHS=0.122 | THS=0.000 | INFO: [Route 35-61] The design met the timing requirement. Phase 12 Post Router Timing | Checksum: 15e28a24d Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 15e28a24d Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 Routing Is Done. Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.707 ; gain = 1.996 write_checkpoint -force $ODIR/post_route Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1626.711 ; gain = 0.000 /var/opt/AXIOM/PROJ/ZYBO/tmds_test/build.vivado/post_route.dcp report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type max -sort_by slack. INFO: [Timing 38-72] No paths found. No timing paths found. report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1000 -nworst 1 -delay_type min -sort_by slack. INFO: [Timing 38-72] No paths found. No timing paths found. report_pulse_width -significant_digits 3 -all_violators INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- | Tool Version : Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 | Date : Tue May 6 05:07:38 2014 | Host : neuromancer.lan running 64-bit Mageia 2 | Command : report_pulse_width -significant_digits 3 -all_violators | Design : top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.10 2014-03-13 ----------------------------------------------------------------------------------- Pulse Width Report exit INFO: [Common 17-206] Exiting Vivado at Tue May 6 05:21:51 2014...