----------------------------------------------------------------------------
--  top.vhd
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2017.2:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.ALL;


entity top is
    port (
	clk : in std_logic;
	--
	data_p : out std_logic;
	data_n : out std_logic
    );
end entity top;

architecture RTL of top is
    signal data : std_logic := '0';
begin
    OBUFDS_inst : OBUFDS
	port map (
	    O => data_p,
	    OB => data_n,
	    I => data );

    data_proc : process(clk)
	variable data_v : std_logic := '0';
    begin
	if rising_edge(clk) then
	    data <= data_v;
	    data_v := not data_v;
	end if;
    end process;
end RTL;