Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
| Date         : Sun Aug  2 10:10:24 2015
| Host         : newhost running 64-bit Mageia 5
| Command      : report_timing_summary -file timing.rpt
| Design       : top
| Device       : 7z010-clg400
| Speed File   : -2  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 2 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     64.674        0.000                      0                   78       -0.052       -0.102                      2                   78        2.000        0.000                       0                    53  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock       Waveform(ns)         Period(ns)      Frequency(MHz)
-----       ------------         ----------      --------------
clk_100     {0.000 4.000}        8.000           125.000         
  pll_clk0  {0.000 40.000}       80.000          12.500          
  pll_clk1  {0.000 33.333}       66.667          15.000          
  pll_fb    {0.000 4.000}        8.000           125.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk_100                                                                                                                                                         2.000        0.000                       0                     1  
  pll_clk0         77.278        0.000                      0                   59        0.036        0.000                      0                   59       39.500        0.000                       0                    37  
  pll_clk1         64.674        0.000                      0                   19       -0.052       -0.102                      2                   19       32.833        0.000                       0                    13  
  pll_fb                                                                                                                                                        6.751        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk_100
  To Clock:  clk_100

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_100
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { clk_100 }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         8.000       6.751      PLLE2_ADV_X0Y1  PLL_inst/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        8.000       44.633     PLLE2_ADV_X0Y1  PLL_inst/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000      PLLE2_ADV_X0Y1  PLL_inst/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000      PLLE2_ADV_X0Y1  PLL_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk0
  To Clock:  pll_clk0

Setup :            0  Failing Endpoints,  Worst Slack       77.278ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       39.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             77.278ns  (required time - arrival time)
  Source:                 FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/WRCLK
                            (rising edge-triggered cell FIFO18E1 clocked by pll_clk0  {rise@0.000ns fall@40.000ns period=80.000ns})
  Destination:            ser_rxtx_inst/rx_data_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by pll_clk0  {rise@0.000ns fall@40.000ns period=80.000ns})
  Path Group:             pll_clk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            80.000ns  (pll_clk0 rise@80.000ns - pll_clk0 rise@0.000ns)
  Data Path Delay:        2.443ns  (logic 0.973ns (39.826%)  route 1.470ns (60.174%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.013ns = ( 85.013 - 80.000 ) 
    Source Clock Delay      (SCD):    5.447ns
    Clock Pessimism Removal (CPR):    0.401ns
  Clock Uncertainty:      0.078ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.140ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_clk0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.422     1.422 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.126     2.548    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.077     2.625 r  PLL_inst/CLKOUT0
                         net (fo=1, routed)           1.290     3.915    pll_clk0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.085     4.000 r  BUFG_inst0/O
                         net (fo=35, routed)          1.447     5.447    FIFO_inst0/clk_100
    RAMB18_X2Y6          FIFO18E1                                     r  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/WRCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X2Y6          FIFO18E1 (Prop_fifo18e1_WRCLK_FULL)
                                                      0.868     6.315 f  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/FULL
                         net (fo=2, routed)           1.184     7.499    ser_rxtx_inst/FULL
    SLICE_X36Y15         LUT4 (Prop_lut4_I2_O)        0.105     7.604 r  ser_rxtx_inst/rx_data[7]_i_1/O
                         net (fo=8, routed)           0.286     7.890    ser_rxtx_inst/rx_data[7]_i_1_n_0
    SLICE_X36Y15         FDRE                                         r  ser_rxtx_inst/rx_data_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk0 rise edge)
                                                     80.000    80.000 r  
    L16                                               0.000    80.000 r  clk_100 (IN)
                         net (fo=0)                   0.000    80.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.356    81.356 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.019    82.375    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.073    82.448 r  PLL_inst/CLKOUT0
                         net (fo=1, routed)           1.171    83.618    pll_clk0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    83.695 r  BUFG_inst0/O
                         net (fo=35, routed)          1.318    85.013    ser_rxtx_inst/ser_clk
    SLICE_X36Y15         FDRE                                         r  ser_rxtx_inst/rx_data_reg[0]/C
                         clock pessimism              0.401    85.414    
                         clock uncertainty           -0.078    85.336    
    SLICE_X36Y15         FDRE (Setup_fdre_C_CE)      -0.168    85.168    ser_rxtx_inst/rx_data_reg[0]
  -------------------------------------------------------------------
                         required time                         85.168    
                         arrival time                          -7.890    
  -------------------------------------------------------------------
                         slack                                 77.278    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 ser_rxtx_inst/rx_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pll_clk0  {rise@0.000ns fall@40.000ns period=80.000ns})
  Destination:            FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/DI[1]
                            (rising edge-triggered cell FIFO18E1 clocked by pll_clk0  {rise@0.000ns fall@40.000ns period=80.000ns})
  Path Group:             pll_clk0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk0 rise@0.000ns - pll_clk0 rise@0.000ns)
  Data Path Delay:        0.691ns  (logic 0.304ns (43.986%)  route 0.387ns (56.014%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.447ns
    Source Clock Delay      (SCD):    5.013ns
    Clock Pessimism Removal (CPR):    0.401ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_clk0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.356     1.356 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.019     2.375    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.073     2.448 r  PLL_inst/CLKOUT0
                         net (fo=1, routed)           1.171     3.618    pll_clk0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077     3.695 r  BUFG_inst0/O
                         net (fo=35, routed)          1.318     5.013    ser_rxtx_inst/ser_clk
    SLICE_X36Y15         FDRE                                         r  ser_rxtx_inst/rx_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y15         FDRE (Prop_fdre_C_Q)         0.304     5.317 r  ser_rxtx_inst/rx_data_reg[1]/Q
                         net (fo=1, routed)           0.387     5.704    FIFO_inst0/Q[1]
    RAMB18_X2Y6          FIFO18E1                                     r  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/DI[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.422     1.422 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.126     2.548    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.077     2.625 r  PLL_inst/CLKOUT0
                         net (fo=1, routed)           1.290     3.915    pll_clk0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.085     4.000 r  BUFG_inst0/O
                         net (fo=35, routed)          1.447     5.447    FIFO_inst0/clk_100
    RAMB18_X2Y6          FIFO18E1                                     r  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/WRCLK
                         clock pessimism             -0.401     5.046    
    RAMB18_X2Y6          FIFO18E1 (Hold_fifo18e1_WRCLK_DI[1])
                                                      0.622     5.668    FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl
  -------------------------------------------------------------------
                         required time                         -5.668    
                         arrival time                           5.704    
  -------------------------------------------------------------------
                         slack                                  0.036    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk0
Waveform(ns):       { 0.000 40.000 }
Period(ns):         80.000
Sources:            { PLL_inst/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     FIFO18E1/WRCLK     n/a            2.170         80.000      77.830     RAMB18_X2Y6     FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/WRCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       80.000      80.000     PLLE2_ADV_X0Y1  PLL_inst/CLKOUT0
Low Pulse Width   Slow    FDRE/C             n/a            0.500         40.000      39.500     SLICE_X36Y17    ser_rxtx_inst/data_v_reg[4]__0/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         40.000      39.500     SLICE_X37Y21    ser_rxtx_inst/cnt_v_reg[0]/C



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk1
  To Clock:  pll_clk1

Setup :            0  Failing Endpoints,  Worst Slack       64.674ns,  Total Violation        0.000ns
Hold  :            2  Failing Endpoints,  Worst Slack       -0.052ns,  Total Violation       -0.102ns
PW    :            0  Failing Endpoints,  Worst Slack       32.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             64.674ns  (required time - arrival time)
  Source:                 FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/RDCLK
                            (rising edge-triggered cell FIFO18E1 clocked by pll_clk1  {rise@0.000ns fall@33.333ns period=66.667ns})
  Destination:            par_loop_inst/rx_ren_reg/D
                            (rising edge-triggered cell FDRE clocked by pll_clk1  {rise@0.000ns fall@33.333ns period=66.667ns})
  Path Group:             pll_clk1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            66.667ns  (pll_clk1 rise@66.667ns - pll_clk1 rise@0.000ns)
  Data Path Delay:        1.913ns  (logic 0.888ns (46.419%)  route 1.025ns (53.581%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.010ns = ( 71.677 - 66.667 ) 
    Source Clock Delay      (SCD):    5.445ns
    Clock Pessimism Removal (CPR):    0.401ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.135ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_clk1 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.422     1.422 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.126     2.548    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.077     2.625 r  PLL_inst/CLKOUT1
                         net (fo=1, routed)           1.290     3.915    pll_clk1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.085     4.000 r  BUFG_inst1/O
                         net (fo=11, routed)          1.445     5.445    FIFO_inst0/CLK
    RAMB18_X2Y6          FIFO18E1                                     r  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/RDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X2Y6          FIFO18E1 (Prop_fifo18e1_RDCLK_EMPTY)
                                                      0.783     6.228 f  FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/EMPTY
                         net (fo=1, routed)           1.025     7.253    FIFO_inst0/EMPTY
    SLICE_X36Y19         LUT2 (Prop_lut2_I0_O)        0.105     7.358 r  FIFO_inst0/rx_ren_i_1/O
                         net (fo=1, routed)           0.000     7.358    par_loop_inst/??
    SLICE_X36Y19         FDRE                                         r  par_loop_inst/rx_ren_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk1 rise edge)
                                                     66.667    66.667 r  
    L16                                               0.000    66.667 r  clk_100 (IN)
                         net (fo=0)                   0.000    66.667    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.356    68.023 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.019    69.042    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.073    69.115 r  PLL_inst/CLKOUT1
                         net (fo=1, routed)           1.171    70.285    pll_clk1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    70.362 r  BUFG_inst1/O
                         net (fo=11, routed)          1.315    71.677    par_loop_inst/CLK
    SLICE_X36Y19         FDRE                                         r  par_loop_inst/rx_ren_reg/C
                         clock pessimism              0.401    72.078    
                         clock uncertainty           -0.076    72.002    
    SLICE_X36Y19         FDRE (Setup_fdre_C_D)        0.030    72.032    par_loop_inst/rx_ren_reg
  -------------------------------------------------------------------
                         required time                         72.032    
                         arrival time                          -7.358    
  -------------------------------------------------------------------
                         slack                                 64.674    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -0.052ns  (arrival time - required time)
  Source:                 par_loop_inst/tx_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pll_clk1  {rise@0.000ns fall@33.333ns period=66.667ns})
  Destination:            FIFO_inst1/bl.fifo_18_inst_bl.fifo_18_bl/DI[1]
                            (rising edge-triggered cell FIFO18E1 clocked by pll_clk1  {rise@0.000ns fall@33.333ns period=66.667ns})
  Path Group:             pll_clk1
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk1 rise@0.000ns - pll_clk1 rise@0.000ns)
  Data Path Delay:        0.599ns  (logic 0.304ns (50.728%)  route 0.295ns (49.272%))
  Logic Levels:           0  
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.441ns
    Source Clock Delay      (SCD):    5.010ns
    Clock Pessimism Removal (CPR):    0.401ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_clk1 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.356     1.356 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.019     2.375    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.073     2.448 r  PLL_inst/CLKOUT1
                         net (fo=1, routed)           1.171     3.618    pll_clk1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077     3.695 r  BUFG_inst1/O
                         net (fo=11, routed)          1.315     5.010    par_loop_inst/CLK
    SLICE_X37Y19         FDRE                                         r  par_loop_inst/tx_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y19         FDRE (Prop_fdre_C_Q)         0.304     5.314 r  par_loop_inst/tx_data_reg[1]/Q
                         net (fo=1, routed)           0.295     5.610    FIFO_inst1/Q[1]
    RAMB18_X2Y8          FIFO18E1                                     r  FIFO_inst1/bl.fifo_18_inst_bl.fifo_18_bl/DI[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk1 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  clk_100 (IN)
                         net (fo=0)                   0.000     0.000    clk_100
    L16                  IBUF (Prop_ibuf_I_O)         1.422     1.422 r  clk_100_IBUF_inst/O
                         net (fo=1, routed)           1.126     2.548    clk_100_IBUF
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.077     2.625 r  PLL_inst/CLKOUT1
                         net (fo=1, routed)           1.290     3.915    pll_clk1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.085     4.000 r  BUFG_inst1/O
                         net (fo=11, routed)          1.441     5.441    FIFO_inst1/CLK
    RAMB18_X2Y8          FIFO18E1                                     r  FIFO_inst1/bl.fifo_18_inst_bl.fifo_18_bl/WRCLK
                         clock pessimism             -0.401     5.040    
    RAMB18_X2Y8          FIFO18E1 (Hold_fifo18e1_WRCLK_DI[1])
                                                      0.622     5.662    FIFO_inst1/bl.fifo_18_inst_bl.fifo_18_bl
  -------------------------------------------------------------------
                         required time                         -5.662    
                         arrival time                           5.610    
  -------------------------------------------------------------------
                         slack                                 -0.052    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk1
Waveform(ns):       { 0.000 33.333 }
Period(ns):         66.667
Sources:            { PLL_inst/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     FIFO18E1/RDCLK     n/a            2.170         66.667      64.497     RAMB18_X2Y6     FIFO_inst0/bl.fifo_18_inst_bl.fifo_18_bl/RDCLK
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       66.667      93.333     PLLE2_ADV_X0Y1  PLL_inst/CLKOUT1
Low Pulse Width   Slow    FDRE/C             n/a            0.500         33.333      32.833     SLICE_X36Y19    par_loop_inst/rx_ren_reg/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         33.333      32.833     SLICE_X36Y19    par_loop_inst/rx_ren_reg/C



---------------------------------------------------------------------------------------------------
From Clock:  pll_fb
  To Clock:  pll_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        6.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_fb
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { PLL_inst/CLKFBOUT }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBIN  n/a            1.249         8.000       6.751      PLLE2_ADV_X0Y1  PLL_inst/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBIN  n/a            52.633        8.000       44.633     PLLE2_ADV_X0Y1  PLL_inst/CLKFBIN



