----------------------------------------------------------------------------
--  shift4_v3.vhd
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity shift is
    port (
	clk	: in std_logic;			-- shift clock
	input	: in std_logic;			-- signal
	--
	data	: out std_logic_vector(3 downto 0)	-- result
    );
end entity shift;


architecture RTL of shift is
begin

    shift_proc : process(clk, input)
	variable reg : std_logic_vector(3 downto 0) := (others => '0');
    begin
	if rising_edge(clk) then
	    reg(3) := reg(2);
	    reg(1) := reg(0);
	end if;
	if falling_edge(clk) then
	    reg(2) := reg(1);
	    reg(0) := input;
	end if;

	data <= reg;

    end process;

end RTL;