----------------------------------------------------------------------------
--  top.vhd (for keep)
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2013.2:
--    mkdir -p build.vivado
--    (cd build.vivado; vivado -mode tcl -source ../vivado.tcl)
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity top is
    port (
	clk_100 : in std_logic		-- input clock to FPGA
    );

end entity top;


architecture RTL of top is

    attribute KEEP : string;

    -- UG901 (V2013.2):
    -- TIP: Register merging can be prevented using the 
    -- KEEP attribute, which prevents optimizations where
    -- signals are either optimized or absorbed into 
    -- logic blocks. 

    -- This attribute instructs the synthesis tool to
    -- keep the signal it was placed on, and that signal 
    -- is placed in the netlist.

    attribute DONT_TOUCH : string;

    -- UG903 (V2013.2):
    -- Set DONT_TOUCH on a leaf cell, hierarchical cell, 
    -- or net object to preserve it during netlist
    -- optimizations.

    -- A net with DONT_TOUCH cannot be absorbed by 
    -- synthesis or implementation.


    attribute MARK_DEBUG : string;

    -- UG903 (V2013.2):
    -- Set MARK_DEBUG on a net in the RTL to preserve 
    -- it and make it visible in the netlist.
    -- This allows it to be connected to the logic 
    -- debug tools at any point in the compilation flow.


    --------------------------------------------------------------------
    -- Clock Signals
    --------------------------------------------------------------------

    attribute DONT_TOUCH of clk_100 : signal is "TRUE";

    --------------------------------------------------------------------
    -- Data Signals
    --------------------------------------------------------------------

    signal data_a : std_logic_vector(7 downto 0);
    signal data_b : std_logic_vector(7 downto 0);

    attribute KEEP of data_a : signal is "TRUE";
    attribute KEEP of data_b : signal is "TRUE";

    attribute DONT_TOUCH of data_a : signal is "TRUE";
    attribute DONT_TOUCH of data_b : signal is "TRUE";

    attribute MARK_DEBUG of data_a : signal is "TRUE";
    attribute MARK_DEBUG of data_b : signal is "TRUE";

begin

    data_proc : process(clk_100)
	variable cnt : unsigned(data_a'range) := (others => '0');
    begin
	if rising_edge(clk_100) then
	    cnt := cnt + "1";
	end if;

	data_a <= std_logic_vector(cnt);
	
	for I in cnt'range loop
	    data_b(I) <= std_logic(cnt(cnt'high - I));
	end loop;
    end process;


end RTL;