----------------------------------------------------------------------------
--  iostd.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt iostd.vhd
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt iostd.ngc
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity top is
    port (
	clk_100 : in std_logic;		-- input clock to FPGA
	--
	btn_c	: in std_logic;		-- button 'center', '1' is pressed
	--
	led	: out std_logic		-- LED: '1' to turn on
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of clk_100: signal is "Y9";
    attribute IOSTANDARD of clk_100: signal is "LVCMOS33";
    attribute PERIOD of clk_100: signal is "10 ns";

    attribute LOC of btn_c: signal is "P16";
    attribute IOSTANDARD of btn_c: signal is "LVCMOS33";

    attribute LOC of led: signal is "U14";
    attribute IOSTANDARD of led: signal is "LVCMOS33";

end entity top;


architecture RTL of top is
begin
    vis_proc : process(clk_100, btn_c)
    begin
	if rising_edge(clk_100) then
	    if btn_c = '1' then
		led <= '1';
	    else
		led <= '0';
	    end if;
	end if;
    end process;

end RTL;