****** Vivado v2017.2.1 (64-bit) **** SW Build 1957588 on Wed Aug 9 16:32:10 MDT 2017 **** IP Build 1948039 on Wed Aug 9 18:19:28 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source vivado.tcl # create_project -part xc7a15tftg256-1 -force vivadoprj vivadoprj # read_vhdl -vhdl2008 init.vhd # synth_design -rtl -top test Command: synth_design -rtl -top test Starting synth_design Using part: xc7a15tftg256-1 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1193.395 ; gain = 75.992 ; free physical = 5257 ; free virtual = 53616 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'test' [/init_bug/init.vhd:25] Parameter INIT bound to: 8'b01010101 INFO: [Synth 8-113] binding component instance 'LUT_inst' to cell 'LUT3' [/init_bug/init.vhd:28] INFO: [Synth 8-256] done synthesizing module 'test' (1#1) [/init_bug/init.vhd:25] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1234.902 ; gain = 117.500 ; free physical = 5266 ; free virtual = 53625 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I1 to constant 0 [/init_bug/init.vhd:28] WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I2 to constant 0 [/init_bug/init.vhd:28] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1234.902 ; gain = 117.500 ; free physical = 5266 ; free virtual = 53624 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a15tftg256-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-141] Inserted 1 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1492.887 ; gain = 375.484 ; free physical = 4988 ; free virtual = 53347 8 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1492.887 ; gain = 375.492 ; free physical = 4988 ; free virtual = 53347 # puts "LUT_inst INIT=[get_property INIT [get_cells LUT_inst]]" LUT_inst INIT=8'h55 # start_gui INFO: [Common 17-206] Exiting Vivado at Mon Sep 11 18:45:53 2017...