----------------------------------------------------------------------------
--  init.vhd
--	Vector Initialization Bug
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;

library unisim;
use unisim.VCOMPONENTS.ALL;

entity test is
    port (Q : out std_logic);
end entity;

architecture RTL of test is
    signal I : std_logic_vector(2 downto 0) := (others => '1');
begin
    LUT_inst : LUT3
	generic map (
	    INIT => x"55" )
	port map (
	    I0 => I(0),
	    I1 => I(1),
	    I2 => I(2),
	    O => Q);

    -- I(0) <= '1';
end RTL;