----------------------------------------------------------------------------
--  i2c_obuft_v3.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt i2c_obuft_v3.prj
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt i2c_obuft_v3.ngc
--  (cd build; promgen -w -b -p bin -o i2c_obuft_v3.bin -u 0 i2c_obuft_v3.bit -data_width 32)
--
--	assumes LM75 (or similar) on PMOD PB1
--	  JB1/1 ... A0
--	  JB1/2 ... A1
--	  JB1/3 ... SDA
--	  JB1/4 ... SCL
--
--	echo lm75 0x49 >/sys/class/i2c-adapter/i2c-0/new_device
--	cat /sys/class/i2c-adapter/i2c-0/0-0049/temp1_*
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity top is
    port (
	pmod	: inout std_logic_vector(3 downto 0)	-- PMOD JB1/1-4
    );

    attribute LOC      : string;	-- Pin Location

    attribute LOC of pmod: signal is "W8 V10 W11 W12";

end entity top;


architecture RTL of top is
    component ps7_stub
	port (
	    i2c_sda_i : in std_ulogic;
	    i2c_sda_o : out std_ulogic;
	    i2c_sda_tn : out std_ulogic;
	    --
	    i2c_scl_i : in std_ulogic;
	    i2c_scl_o : out std_ulogic;
	    i2c_scl_tn : out std_ulogic
	);
    end component ps7_stub;

    component IBUF
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    IBUF_DELAY_VALUE : string := "0";
	    IBUF_LOW_PWR : boolean := TRUE;
	    IFD_DELAY_VALUE : string := "AUTO";
	    IOSTANDARD : string := "DEFAULT"
	);
	port (
	    O : out std_ulogic;
	    I : in std_ulogic
	);
    end component IBUF;

    component OBUF
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    DRIVE : integer := 12;
	    IOSTANDARD : string := "DEFAULT";
	    SLEW : string := "SLOW"
	);
	port (
	    O : out std_ulogic;
	    I : in std_ulogic
	);
    end component OBUF;

    component OBUFT
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    DRIVE : integer := 12;
	    IOSTANDARD : string := "DEFAULT";
	    SLEW : string := "SLOW"
	);
	port (
	    O : out std_ulogic;
	    I : in std_ulogic;
	    T : in std_ulogic
	);
    end component OBUFT;

    signal sda_i : std_ulogic;
    signal sda_o : std_ulogic;
    signal sda_tn : std_ulogic;
    signal sda_t : std_ulogic;

    signal scl_i : std_ulogic;
    signal scl_o : std_ulogic;
    signal scl_tn : std_ulogic;
    signal scl_t : std_ulogic;

begin
    ps7_stub_inst : ps7_stub
	port map ( i2c_sda_i => sda_i, i2c_sda_o => sda_o, i2c_sda_tn => sda_tn,
		   i2c_scl_i => scl_i, i2c_scl_o => scl_o, i2c_scl_tn => scl_tn );

    -- lm75 address
    OBUF_A0_inst : OBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => '0', O => pmod(0) );
    OBUF_A1_inst : OBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => '0', O => pmod(1) );


    -- sda
    sda_t <= '1' when sda_tn = '0' else '0';
    OBUFT_0_inst : OBUFT
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => '0', T => sda_t, O => pmod(2) );
    IBUF_0_inst : IBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => pmod(2), O => sda_i );

    -- scl
    scl_t <= '1' when scl_tn = '0' else '0';
    OBUFT_1_inst : OBUFT
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => '0', T => scl_t, O => pmod(3) );
    IBUF_1_inst : IBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => pmod(3), O => scl_i );

end RTL;