----------------------------------------------------------------------------
--  flipflop.vhd
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--	(mkdir -p fuse; cd fuse; fuse flipflop -prj ../flipflop.prj -o isim.elf)
--	(cd fuse; ./isim.elf -gui)
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity flipflop is
    port (
    	clk	: in std_logic;		-- clock
    	--
    	output  : out std_logic		-- result
    );
end entity flipflop;

architecture RTL of flipflop is
begin

    flipflop_proc : process(clk)
	variable val : std_logic := '0';
    begin

	if rising_edge(clk) then
	    if val = '1' then
		val := '0';
	    else
		val := '1';
	    end if;
	end if;

	output <= val;

    end process;

end;