----------------------------------------------------------------------------
--  dna.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_mixed.opt dna.prj
--  ln -s ../dna.ucf build/ # work around xflow bug
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt dna.ngc
--
----------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity divider is
    generic (
	RATIO : integer := 20000000
    );
    port (
	clk_in	: in std_logic;		-- input clock
	--
	enable	: in std_logic;		-- enable divider
	--
	clk_out	: out std_logic		-- output clk_in
    );

    attribute buffer_type : string;	-- buffer type

    attribute buffer_type of clk_out : signal is "bufg";

end entity divider;

architecture RTL of divider is
begin
    divide_proc : process(clk_in, enable)
    variable count : integer range 0 to RATIO - 1;
    begin
	if rising_edge(clk_in) then	-- clk
	    if enable = '1' then	-- enabled
		if count = RATIO - 1 then
		    count := 0;
		else
		    count := count + 1;
		end if;

		if count < RATIO / 2 then
		    clk_out <= '0';
		else
		    clk_out <= '1';
		end if;
	    end if;
	end if;
    end process;
end RTL;



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library UNISIM;
use UNISIM.VComponents.all;


entity dna is
    port (
	clk_100 : in std_logic;		-- input clock to FPGA
	--
	led	: out std_logic_vector(7 downto 0)	-- LED: '1' to turn on
    );

end entity;


architecture RTL of dna is

    component DNA_PORT
	generic (
	    SIM_DNA_VALUE : bit_vector := X"000000000000000"
	);
	port (
	    DOUT : out std_ulogic;
	    CLK : in std_ulogic;
	    DIN : in std_ulogic;
	    READ : in std_ulogic;
	    SHIFT : in std_ulogic
	);
    end component DNA_PORT;

    signal reset : std_logic;
    signal reset_n : std_logic;

    signal ser_clk : std_logic;
    signal ser_data : std_logic;

begin
    ps7_stub_inst : entity work.ps7_stub;

    dna_inst : DNA_PORT
	generic map (
	    SIM_DNA_VALUE => X"123456789ABCDEF"
	)
	port map (
	    CLK => ser_clk,
	    DOUT => ser_data,
	    DIN => ser_data,

	    READ => reset,
	    SHIFT => '1' );

    div_inst_100 : entity work.divider
	port map ( clk_in => clk_100,
		   enable => reset_n,
		   clk_out => ser_clk);


    reset_proc : process(clk_100)
	variable cnt : natural := 1000000;
    begin
	if rising_edge(clk_100) then
	    if cnt > 0 then
		reset <= '1';
		cnt := cnt - 1;
	    else
		reset <= '0';
	    end if;
	end if;
    end process;

    reset_n <= '0' when reset = '1' else '1';

    vis_proc : process(ser_clk, ser_data)
	variable buf : std_logic_vector(7 downto 0) := "10101010";
    begin
	if rising_edge(ser_clk) then
	    buf := buf(6 downto 0) & ser_data;
	end if;

	led <= buf;
    end process;

end RTL;