----------------------------------------------------------------------------
--  top.vhd (for delay_test)
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2013.2:
--    mkdir -p build.vivado
--    (cd build.vivado; vivado -mode tcl -source ../vivado.tcl)
--    (cd build.vivado; promgen -w -b -p bin delay_test.bit -data_width 32)
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.VCOMPONENTS.all;


entity top is
    port (
	clk_100 : in std_logic;			-- input clock to FPGA
	--
	btn_l : in std_logic;	-- Button: '1' is pressed
	btn_c : in std_logic;	-- Button: '1' is pressed
	btn_r : in std_logic;	-- Button: '1' is pressed
	btn_u : in std_logic;	-- Button: '1' is pressed
	btn_d : in std_logic;	-- Button: '1' is pressed
	--
	swi : in std_logic_vector(7 downto 0);
	led : out std_logic_vector(7 downto 0)
    );

end entity top;


architecture RTL of top is

    --------------------------------------------------------------------
    -- PLL Signals
    --------------------------------------------------------------------

    signal pll_fbout : std_logic;
    signal pll_fbin : std_logic;

    signal pll_locked : std_logic;

    signal pll_clk0 : std_logic;
    signal pll_clk1 : std_logic;

    --------------------------------------------------------------------
    -- IDELAY CTRL Signals
    --------------------------------------------------------------------

    signal idelay_ref_clk : std_logic;

    --------------------------------------------------------------------
    -- IDELAY Signals
    --------------------------------------------------------------------

    signal data_ser : std_logic;
    signal data_ser_del : std_logic;

    signal idelay_ce : std_logic;
    signal idelay_inc : std_logic;
    signal idelay_ld : std_logic;
    signal idelay_ldpipeen : std_logic;

    signal idelay_val : std_logic_vector(4 downto 0);
    signal idelay_oval : std_logic_vector(4 downto 0);
    signal idelay_rst : std_logic;

    signal idelay_valid : std_logic;
    signal idelay_clk : std_logic;

    --------------------------------------------------------------------
    -- Adjust Signals
    --------------------------------------------------------------------

    signal adj_clk : std_logic;

    signal btn_feedback : std_logic;

begin

    --------------------------------------------------------------------
    -- PLL and IDELAYCTRL
    --------------------------------------------------------------------

    pll_inst : PLLE2_BASE
	generic map (
	    CLKIN1_PERIOD => 10.0,
	    CLKFBOUT_MULT => 10,
	    CLKOUT0_DIVIDE => 1000/200, -- 200MHz REF clock
	    CLKOUT1_DIVIDE => 1000/10,	--  10MHz TAP clock
	    DIVCLK_DIVIDE => 1 )
	port map (
	    CLKIN1 => clk_100,
	    CLKFBOUT => pll_fbout,
	    CLKFBIN => pll_fbin,

	    CLKOUT0 => pll_clk0,
	    CLKOUT1 => pll_clk1,

	    LOCKED => pll_locked,
	    PWRDWN => '0',
	    RST => '0' );

    pll_fbin <= pll_fbout;

    BUFG_inst0 : BUFG
    	port map (
    	    I => pll_clk0,
    	    O => idelay_ref_clk );

    BUFG_inst1 : BUFG
    	port map (
    	    I => pll_clk1,
    	    O => idelay_clk );

    IDELAYCTRL_inst : IDELAYCTRL
	port map (
	    RDY => idelay_valid,	-- 1-bit output indicates validity of the REFCLK
	    REFCLK => idelay_ref_clk,	-- 1-bit reference clock input
	    RST => '0' );		-- 1-bit reset input

    --------------------------------------
    -- 32-TAP	DELAY: IDELAY PRIMITIVE --
    --------------------------------------

    IDELAY_inst : IDELAYE2
	generic map (
	    HIGH_PERFORMANCE_MODE   => "FALSE",
	    IDELAY_TYPE		    => "VAR_LOAD",
	    IDELAY_VALUE	    => 2#10101#,
	    REFCLK_FREQUENCY	    => 200.0,
	    SIGNAL_PATTERN	    => "DATA" )
	port map (
	    IDATAIN	=> data_ser,
	    DATAIN	=> '0',
	    DATAOUT	=> data_ser_del,
	    CINVCTRL	=> '0',
	    CNTVALUEIN	=> idelay_val,
	    CNTVALUEOUT => idelay_oval,
	    LD		=> idelay_ld,
	    LDPIPEEN	=> idelay_ldpipeen,
	    C		=> idelay_clk,
	    CE		=> idelay_ce,
	    INC		=> idelay_inc,
	    REGRST	=> idelay_rst );

    --------------------------------------------------------------------
    -- Switch Control Input 
    --------------------------------------------------------------------

    idelay_inc <= swi(7);
    idelay_ldpipeen <= swi(6);
    data_ser <= swi(5);
    idelay_val <= swi(4 downto 0);

    --------------------------------------------------------------------
    -- LED Status output
    --------------------------------------------------------------------

    led(7) <= idelay_valid and pll_locked;
    led(6) <= btn_feedback;
    led(5) <= data_ser_del;
    led(4 downto 0) <= idelay_oval;

    --------------------------------------------------------------------
    -- Button Input
    --------------------------------------------------------------------

    adj_proc : process(idelay_clk)

	variable count_v : natural;

	type adj_state is (
	    idle_s, wait_s,
	    btnu_s, btnd_s, btnl_s, btnr_s, btnc_s );

	variable state : adj_state := idle_s;

	variable idelay_ce_v : std_logic := '0';
	variable idelay_ld_v : std_logic := '0';
	variable idelay_rst_v : std_logic := '0';

    begin

	btn_feedback <= '0';

	if rising_edge(idelay_clk) then
	    case state is
		when idle_s =>
		    if btn_c = '1' then
			state := btnc_s;
		    elsif btn_u = '1' then
			state := btnu_s;
		    elsif btn_d = '1' then
			state := btnd_s;
		    elsif btn_l = '1' then
			state := btnl_s;
		    elsif btn_r = '1' then
			state := btnr_s;
		    end if;

		when wait_s =>
		    btn_feedback <= '1';
		    if count_v = 0 then
			if  btn_c = '0' and
			    btn_u = '0' and
			    btn_d = '0' and
			    btn_l = '0' and
			    btn_r = '0' then
			    state := idle_s;
			else
			    count_v := 2 ** 20;
			end if;
		    else
			count_v := count_v - 1;
		    end if;

		when others =>
		    count_v := 2 ** 20;
		    state := wait_s;

	    end case;
	end if;

	if falling_edge(idelay_clk) then
	    case state is
		when btnc_s =>
		    idelay_ce_v := '1';

		when btnu_s =>
		    null;

		when btnd_s =>
		    null;

		when btnl_s =>
		    idelay_ld_v := '1';

		when btnr_s =>
		    idelay_rst_v := '1';

		when others =>
		    idelay_ce_v := '0';
		    idelay_ld_v := '0';
		    idelay_rst_v := '0';
		    null;

	    end case;
	end if;

	idelay_ce <= idelay_ce_v;
	idelay_rst <= idelay_rst_v;
	idelay_ld <= idelay_ld_v;

    end process;

end RTL;