----------------------------------------------------------------------------
--  cnt8.vhd
--	Limited 8bit Counter (Fast)
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;


entity cnt8 is
    generic (
	LIMIT : integer := 250 );
    port (
	C : in std_logic;
	R : in std_logic;
	Q : out std_logic_vector(7 downto 0) );
end entity;

architecture RTL of cnt8 is

    constant CL : std_logic_vector(7 downto 0) :=
	std_logic_vector(to_unsigned(LIMIT, 8));

    signal SLI : std_logic_vector(7 downto 0);
    signal SLQ : std_logic_vector(7 downto 0);
    signal SLC : std_logic_vector(7 downto 0);

    signal RQ : std_logic_vector(7 downto 0) := x"00";

    signal SR : std_logic;

begin

    GEN_SLUT : for I in 0 to 7 generate
    begin
	SLQ(I) <= SLI(I) xor SLC(I);
	SLC(I) <= and SLI(I-1 downto 0);
	SLI(I) <= RQ(I);
    end generate;

    reg_proc : process(C)
    begin
        if rising_edge(C) then
	    if SR = '1' then
		RQ <= x"00";		-- reset
	    else
		RQ <= SLQ;
	    end if;
        end if;
    end process;

    SR <= '1' when RQ = CL else R;	-- reset

    Q <= RQ;

end RTL;