----------------------------------------------------------------------------
--  top.vhd
--	Simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2017.2:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
--
--  Simulation:
--    mkdir -p sim.vivado
--    (cd sim.vivado && xvhdl -vhdl2008 ../top.vhd ../dsp48_wrap.vhd)
--    (cd sim.vivado && xelab -debug typical top -s sim)
--    (cd sim.vivado && xsim sim -tclbatch ../sim.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library UNISIM;
use UNISIM.vcomponents.ALL;

library STD;
use STD.textio.ALL;


entity top is
    port (
	clk : in std_logic;
	Q : out std_logic_vector(47 downto 0) );
end entity top;


architecture RTL of top is

    constant A1 : std_logic_vector(29 downto 0) :=
	"001100110011001100110011001100";
    constant A2 : std_logic_vector(29 downto 0) :=
	"001111000011110000111100001111";

    signal cea : std_logic := '0';
    signal inmode : std_logic_vector(4 downto 0) := "00000";

    signal A : std_logic_vector(29 downto 0);
    signal B : std_logic_vector(17 downto 0);
    signal P : std_logic_vector(47 downto 0);

begin


    DSP48E1_inst : entity work.dsp48_wrap
	generic map (
	    USE_MULT => "MULTIPLY",	-- "NONE", "MULTIPLY", "DYNAMIC"
	    AREG => 2,			-- Pipeline stages for A (0, 1 or 2)
	    PREG => 0,			-- Pipeline stages for P (0 or 1)
	    ACASCREG => 2 )		-- Pipeline stages A/ACIN to ACOUT (0, 1 or 2)
	port map (
	    CLK => clk,			-- 1-bit input: Clock input
	    A => A,			-- 30-bit input: A data input
	    B => B,			-- 18-bit input: B data input
	    CEA1 => cea,		-- 1-bit input: CE input for 1st stage AREG
	    CEA2 => cea,		-- 1-bit input: CE input for 2nd stage AREG
	    INMODE => inmode,		-- 5-bit input: INMODE control input
	    ALUMODE => "0000",		-- 4-bit input: ALU control input
	    OPMODE => "0000101", 	-- 7-bit input: Operation mode input
	    P => P );			-- 48-bit output: Primary data output

    B <= (0=>'1', others => '0');

    load_proc : process(clk)
	type state_t is (LOAD_A2, LOAD_A1, HOLD);

	variable state : state_t := LOAD_A2;
    begin
	if rising_edge(clk) then
	    case state is
		when LOAD_A2 =>
		    A <= A2;
		    cea <= '1';
		    state := LOAD_A1;

		when LOAD_A1 =>
		    A <= A1;
		    cea <= '1';
		    state := HOLD;

		when HOLD =>
		    cea <= '0';
	    end case;		
	end if;
    end process;

    switch_proc : process(clk)
	variable mode : std_logic := '1';
    begin
	if rising_edge(clk) then
	    inmode <= "0000" & mode;
	    mode := not mode;

	    Q <= P;
	end if;
    end process;

    debug_proc : process(clk)
	variable info : line;
    begin
	if rising_edge(clk) then
	    write(info, string'(" A="));
	    write(info, A);
	    write(info, string'(" P="));
	    write(info, P);
	    writeline(output, info);
	end if;
    end process;


end RTL;