----------------------------------------------------------------------------
--  case.vhd
--	Simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt case.vhd
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt case.ngc
--  (cd build; promgen -w -b -p bin -o case.bin -u 0 case.bit -data_width 32)
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity top is
    port (
	clk_100 : in std_logic;				-- input clock to FPGA
	--
	swi	: in std_logic_vector(3 downto 0);	-- Switch: '1' is up
	--
	led	: out std_logic				-- LED: '1' to turn on
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of clk_100: signal is "Y9";
    attribute IOSTANDARD of clk_100: signal is "LVCMOS33";
    attribute PERIOD of clk_100: signal is "10 ns";

    attribute LOC of swi: signal is "F21 H22 G22 F22";
    attribute IOSTANDARD of swi: signal is "LVCMOS33";

    attribute LOC of led: signal is "T22";
    attribute IOSTANDARD of led: signal is "LVCMOS33";

end entity top;


architecture RTL of top is
    signal sig : std_logic;
begin
    sel_proc : process(swi, sig)
    begin 
	case swi(1 downto 0) is
	    when "00" => sig <= '0';
	    when "01" => sig <= '1';
	    when "10" => sig <= swi(2);
	    when "11" => sig <= swi(3);
	    -- when others => sig <= '0';
	end case;

	led <= sig;
    end process;

end RTL;