----------------------------------------------------------------------------
--  blink.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  ISE 14.6:
--    xflow -p xc7z020clg484-1 -wd build.ise -synth xst_mixed.opt blink.prj
--    ln -s ../blink.ucf build.ise/ # work around xflow bug
--    xflow -p xc7z020clg484-1 -wd build.ise -implement balanced.opt -config bitgen.opt blink.ngc
--
--  Vivado 2013.2:
--    mkdir -p build.vivado
--    (cd build.vivado; vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity blink is
    port (
	led	: out std_logic		-- LED: '1' to turn on
    );
end entity blink;


architecture RTL of blink is
    signal ps_fclk : std_logic_vector(3 downto 0);

    attribute buffer_type : string;
    attribute buffer_type of ps_fclk: signal is "bufg";

begin
    ps7_stub_inst : entity work.ps7_stub
	port map (
	    ps_fclk => ps_fclk
	);

    blink_proc : process(ps_fclk(0))
	variable count : natural := 0;
    begin
	if rising_edge(ps_fclk(0)) then
	    if count < 10_000_000 then
		count := count + 1;
	    else
		count := 0;
	    end if;
	end if;
	
	if count < 5_000_000 then
	    led <= '1';
	else
	    led <= '0';
	end if;
    end process;

end RTL;