---------------------------------------------------------------------------- -- top.vhd (for axi3_test) -- ZedBoard simple VHDL example -- Version 1.1 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- Vivado 2013.2: -- mkdir -p build.vivado -- (cd build.vivado; vivado -mode tcl -source ../vivado.tcl) -- (cd build.vivado; promgen -w -b -p bin -u 0 axi3_test.bit -data_width 32) -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.all; use work.axi3s_pkg.all; -- AXI3 Slave Interface entity top is port ( clk_100_in : in std_logic; -- input clock to FPGA -- swi : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0) ); end entity top; architecture RTL of top is attribute DONT_TOUCH : string; -------------------------------------------------------------------- -- PS7 AXI Slave Signals -------------------------------------------------------------------- signal s_axi0_aclk : std_ulogic; signal s_axi0_areset_n : std_ulogic; signal s_axi0_wi : axi3s_write_in_r; signal s_axi0_wo : axi3s_write_out_r; signal s_axi1_aclk : std_ulogic; signal s_axi1_areset_n : std_ulogic; signal s_axi1_wi : axi3s_write_in_r; signal s_axi1_wo : axi3s_write_out_r; signal s_axi2_aclk : std_ulogic; signal s_axi2_areset_n : std_ulogic; signal s_axi2_wi : axi3s_write_in_r; signal s_axi2_wo : axi3s_write_out_r; signal s_axi3_aclk : std_ulogic; signal s_axi3_areset_n : std_ulogic; signal s_axi3_wi : axi3s_write_in_r; signal s_axi3_wo : axi3s_write_out_r; -------------------------------------------------------------------- -- Clock Signals -------------------------------------------------------------------- signal clk_100 : std_ulogic; attribute dont_touch of clk_100 : signal is "true"; -------------------------------------------------------------------- -- AXI MMCM Signals -------------------------------------------------------------------- signal axi_mmcm_reset_n : std_ulogic; signal axi_mmcm : std_logic_vector(6 downto 0); signal axi_mmcm_locked : std_ulogic; signal axi0_clk : std_ulogic; signal axi1_clk : std_ulogic; signal axi2_clk : std_ulogic; signal axi3_clk : std_ulogic; signal data_clk : std_ulogic; signal addr_clk : std_ulogic; attribute dont_touch of axi_mmcm : signal is "true"; -------------------------------------------------------------------- -- Writer Signals -------------------------------------------------------------------- signal data0_clk : std_ulogic; signal data0_enable : std_ulogic; signal data0_in : std_logic_vector(63 downto 0); signal data0_full : std_ulogic; signal data0_reset_n : std_ulogic; signal addr0_clk : std_ulogic; signal addr0_enable : std_ulogic; signal addr0_in : std_logic_vector(31 downto 0); signal addr0_full : std_ulogic; signal addr0_reset_n : std_ulogic; signal writer0_state : std_logic_vector(7 downto 0); signal data1_clk : std_ulogic; signal data1_enable : std_ulogic; signal data1_in : std_logic_vector(63 downto 0); signal data1_full : std_ulogic; signal data1_reset_n : std_ulogic; signal addr1_clk : std_ulogic; signal addr1_enable : std_ulogic; signal addr1_in : std_logic_vector(31 downto 0); signal addr1_full : std_ulogic; signal addr1_reset_n : std_ulogic; signal writer1_state : std_logic_vector(7 downto 0); signal data2_clk : std_ulogic; signal data2_enable : std_ulogic; signal data2_in : std_logic_vector(63 downto 0); signal data2_full : std_ulogic; signal data2_reset_n : std_ulogic; signal addr2_clk : std_ulogic; signal addr2_enable : std_ulogic; signal addr2_in : std_logic_vector(31 downto 0); signal addr2_full : std_ulogic; signal addr2_reset_n : std_ulogic; signal writer2_state : std_logic_vector(7 downto 0); signal data3_clk : std_ulogic; signal data3_enable : std_ulogic; signal data3_in : std_logic_vector(63 downto 0); signal data3_full : std_ulogic; signal data3_reset_n : std_ulogic; signal addr3_clk : std_ulogic; signal addr3_enable : std_ulogic; signal addr3_in : std_logic_vector(31 downto 0); signal addr3_full : std_ulogic; signal addr3_reset_n : std_ulogic; signal writer3_state : std_logic_vector(7 downto 0); begin -------------------------------------------------------------------- -- PS7 Interface -------------------------------------------------------------------- ps7_stub_inst : entity work.ps7_stub port map ( s_axi0_aclk => s_axi0_aclk, s_axi0_areset_n => s_axi0_areset_n, -- s_axi0_awid => s_axi0_wi.awid, s_axi0_awaddr => s_axi0_wi.awaddr, s_axi0_awburst => s_axi0_wi.awburst, s_axi0_awlen => s_axi0_wi.awlen, s_axi0_awsize => s_axi0_wi.awsize, s_axi0_awprot => s_axi0_wi.awprot, s_axi0_awvalid => s_axi0_wi.awvalid, s_axi0_awready => s_axi0_wo.awready, s_axi0_wacount => s_axi0_wo.wacount, -- s_axi0_wid => s_axi0_wi.wid, s_axi0_wdata => s_axi0_wi.wdata, s_axi0_wstrb => s_axi0_wi.wstrb, s_axi0_wlast => s_axi0_wi.wlast, s_axi0_wvalid => s_axi0_wi.wvalid, s_axi0_wready => s_axi0_wo.wready, s_axi0_wcount => s_axi0_wo.wcount, -- s_axi0_bid => s_axi0_wo.bid, s_axi0_bresp => s_axi0_wo.bresp, s_axi0_bvalid => s_axi0_wo.bvalid, s_axi0_bready => s_axi0_wi.bready, -- s_axi1_aclk => s_axi1_aclk, s_axi1_areset_n => s_axi1_areset_n, -- s_axi1_awid => s_axi1_wi.awid, s_axi1_awaddr => s_axi1_wi.awaddr, s_axi1_awburst => s_axi1_wi.awburst, s_axi1_awlen => s_axi1_wi.awlen, s_axi1_awsize => s_axi1_wi.awsize, s_axi1_awprot => s_axi1_wi.awprot, s_axi1_awvalid => s_axi1_wi.awvalid, s_axi1_awready => s_axi1_wo.awready, s_axi1_wacount => s_axi1_wo.wacount, -- s_axi1_wid => s_axi1_wi.wid, s_axi1_wdata => s_axi1_wi.wdata, s_axi1_wstrb => s_axi1_wi.wstrb, s_axi1_wlast => s_axi1_wi.wlast, s_axi1_wvalid => s_axi1_wi.wvalid, s_axi1_wready => s_axi1_wo.wready, s_axi1_wcount => s_axi1_wo.wcount, -- s_axi1_bid => s_axi1_wo.bid, s_axi1_bresp => s_axi1_wo.bresp, s_axi1_bvalid => s_axi1_wo.bvalid, s_axi1_bready => s_axi1_wi.bready, -- s_axi2_aclk => s_axi2_aclk, s_axi2_areset_n => s_axi2_areset_n, -- s_axi2_awid => s_axi2_wi.awid, s_axi2_awaddr => s_axi2_wi.awaddr, s_axi2_awburst => s_axi2_wi.awburst, s_axi2_awlen => s_axi2_wi.awlen, s_axi2_awsize => s_axi2_wi.awsize, s_axi2_awprot => s_axi2_wi.awprot, s_axi2_awvalid => s_axi2_wi.awvalid, s_axi2_awready => s_axi2_wo.awready, s_axi2_wacount => s_axi2_wo.wacount, -- s_axi2_wid => s_axi2_wi.wid, s_axi2_wdata => s_axi2_wi.wdata, s_axi2_wstrb => s_axi2_wi.wstrb, s_axi2_wlast => s_axi2_wi.wlast, s_axi2_wvalid => s_axi2_wi.wvalid, s_axi2_wready => s_axi2_wo.wready, s_axi2_wcount => s_axi2_wo.wcount, -- s_axi2_bid => s_axi2_wo.bid, s_axi2_bresp => s_axi2_wo.bresp, s_axi2_bvalid => s_axi2_wo.bvalid, s_axi2_bready => s_axi2_wi.bready, -- s_axi3_aclk => s_axi3_aclk, s_axi3_areset_n => s_axi3_areset_n, -- s_axi3_awid => s_axi3_wi.awid, s_axi3_awaddr => s_axi3_wi.awaddr, s_axi3_awburst => s_axi3_wi.awburst, s_axi3_awlen => s_axi3_wi.awlen, s_axi3_awsize => s_axi3_wi.awsize, s_axi3_awprot => s_axi3_wi.awprot, s_axi3_awvalid => s_axi3_wi.awvalid, s_axi3_awready => s_axi3_wo.awready, s_axi3_wacount => s_axi3_wo.wacount, -- s_axi3_wid => s_axi3_wi.wid, s_axi3_wdata => s_axi3_wi.wdata, s_axi3_wstrb => s_axi3_wi.wstrb, s_axi3_wlast => s_axi3_wi.wlast, s_axi3_wvalid => s_axi3_wi.wvalid, s_axi3_wready => s_axi3_wo.wready, s_axi3_wcount => s_axi3_wo.wcount, -- s_axi3_bid => s_axi3_wo.bid, s_axi3_bresp => s_axi3_wo.bresp, s_axi3_bvalid => s_axi3_wo.bvalid, s_axi3_bready => s_axi3_wi.bready ); -------------------------------------------------------------------- -- Clock Buffer -------------------------------------------------------------------- BUFGP_inst : BUFGP port map ( O => clk_100, I => clk_100_in ); -------------------------------------------------------------------- -- AXI MMCM -------------------------------------------------------------------- axi_mmcm_inst : entity work.axi_mmcm port map ( clk_in => clk_100, reset_n => axi_mmcm_reset_n, -- mmcm_clk => axi_mmcm, -- mmcm_locked => axi_mmcm_locked ); axi0_clk <= axi_mmcm(0); axi1_clk <= axi_mmcm(1); axi2_clk <= axi_mmcm(2); axi3_clk <= axi_mmcm(3); data_clk <= axi_mmcm(4); addr_clk <= axi_mmcm(5); axi_mmcm_reset_n <= swi(0); -------------------------------------------------------------------- -- LED Status output -------------------------------------------------------------------- led(0) <= axi_mmcm_locked; led(1) <= '0'; led(3 downto 2) <= swi(3 downto 2); led(4) <= data0_full; led(5) <= data1_full; led(6) <= data2_full; led(7) <= data3_full; -------------------------------------------------------------------- -- AXIHP Writer 0 -------------------------------------------------------------------- axihp_writer_inst0 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, ADDR_MASK => x"000FFFFF", ADDR_DATA => x"1B000000" ) port map ( m_axi_aclk => s_axi0_aclk, m_axi_areset_n => s_axi0_areset_n, enable => swi(4), -- m_axi_wo => s_axi0_wi, m_axi_wi => s_axi0_wo, -- data_clk => data0_clk, data_enable => data0_enable, data_in => data0_in, data_full => data0_full, -- addr_clk => addr0_clk, addr_enable => addr0_enable, addr_in => addr0_in, addr_full => addr0_full, -- writer_state => writer0_state ); s_axi0_aclk <= axi0_clk; data_gen_inst0 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data0_clk, reset_n => data0_reset_n, enable => data0_enable, -- data_min => x"00000000", data_inc => x"00000001", data_max => x"0FFFFFFF", -- data => data0_in(31 downto 0) ); data0_in(63 downto 32) <= x"00000000"; data0_clk <= data_clk; data0_enable <= swi(2) and not data0_full; data0_reset_n <= swi(1); addr_gen_inst0 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr0_clk, reset_n => addr0_reset_n, enable => addr0_enable, -- data_min => x"1B000000", data_inc => x"00000080", data_max => x"1B0FFF80", -- data => addr0_in ); addr0_clk <= addr_clk; addr0_enable <= swi(3) and not addr0_full; addr0_reset_n <= swi(1); -------------------------------------------------------------------- -- AXIHP Writer 1 -------------------------------------------------------------------- axihp_writer_inst1 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, ADDR_MASK => x"000FFFFF", ADDR_DATA => x"1B200000" ) port map ( m_axi_aclk => s_axi1_aclk, m_axi_areset_n => s_axi1_areset_n, enable => swi(5), -- m_axi_wo => s_axi1_wi, m_axi_wi => s_axi1_wo, -- data_clk => data1_clk, data_enable => data1_enable, data_in => data1_in, data_full => data1_full, -- addr_clk => addr1_clk, addr_enable => addr1_enable, addr_in => addr1_in, addr_full => addr1_full, -- writer_state => writer1_state ); s_axi1_aclk <= axi1_clk; data_gen_inst1 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data1_clk, reset_n => data1_reset_n, enable => data1_enable, -- data_min => x"20000000", data_inc => x"00000001", data_max => x"2FFFFFFF", -- data => data1_in(31 downto 0) ); data1_in(63 downto 32) <= x"11111111"; data1_clk <= data_clk; data1_enable <= swi(2) and not data1_full; data1_reset_n <= swi(1); addr_gen_inst1 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr1_clk, reset_n => addr1_reset_n, enable => addr1_enable, -- data_min => x"1B200000", data_inc => x"00000080", data_max => x"1B2FFF80", -- data => addr1_in ); addr1_clk <= addr_clk; addr1_enable <= swi(3) and not addr1_full; addr1_reset_n <= swi(1); -------------------------------------------------------------------- -- AXIHP Writer 2 -------------------------------------------------------------------- axihp_writer_inst2 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, ADDR_MASK => x"000FFFFF", ADDR_DATA => x"1B400000" ) port map ( m_axi_aclk => s_axi2_aclk, m_axi_areset_n => s_axi2_areset_n, enable => swi(6), -- m_axi_wo => s_axi2_wi, m_axi_wi => s_axi2_wo, -- data_clk => data2_clk, data_enable => data2_enable, data_in => data2_in, data_full => data2_full, -- addr_clk => addr2_clk, addr_enable => addr2_enable, addr_in => addr2_in, addr_full => addr2_full, -- writer_state => writer2_state ); s_axi2_aclk <= axi2_clk; data_gen_inst2 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data2_clk, reset_n => data2_reset_n, enable => data2_enable, -- data_min => x"40000000", data_inc => x"00000001", data_max => x"4FFFFFFF", -- data => data2_in(31 downto 0) ); data2_in(63 downto 32) <= x"22222222"; data2_clk <= data_clk; data2_enable <= swi(2) and not data2_full; data2_reset_n <= swi(1); addr_gen_inst2 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr2_clk, reset_n => addr2_reset_n, enable => addr2_enable, -- data_min => x"1B400000", data_inc => x"00000080", data_max => x"1B4FFF80", -- data => addr2_in ); addr2_clk <= addr_clk; addr2_enable <= swi(3) and not addr2_full; addr2_reset_n <= swi(1); -------------------------------------------------------------------- -- AXIHP Writer 3 -------------------------------------------------------------------- axihp_writer_inst3 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, ADDR_MASK => x"000FFFFF", ADDR_DATA => x"1B600000" ) port map ( m_axi_aclk => s_axi3_aclk, m_axi_areset_n => s_axi3_areset_n, enable => swi(7), -- m_axi_wo => s_axi3_wi, m_axi_wi => s_axi3_wo, -- data_clk => data3_clk, data_enable => data3_enable, data_in => data3_in, data_full => data3_full, -- addr_clk => addr3_clk, addr_enable => addr3_enable, addr_in => addr3_in, addr_full => addr3_full, -- writer_state => writer3_state ); s_axi3_aclk <= axi3_clk; data_gen_inst3 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data3_clk, reset_n => data3_reset_n, enable => data3_enable, -- data_min => x"60000000", data_inc => x"00000001", data_max => x"6FFFFFFF", -- data => data3_in(31 downto 0) ); data3_in(63 downto 32) <= x"33333333"; data3_clk <= data_clk; data3_enable <= swi(2) and not data3_full; data3_reset_n <= swi(1); addr_gen_inst3 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr3_clk, reset_n => addr3_reset_n, enable => addr3_enable, -- data_min => x"1B600000", data_inc => x"00000080", data_max => x"1B6FFF80", -- data => addr3_in ); addr3_clk <= addr_clk; addr3_enable <= swi(3) and not addr3_full; addr3_reset_n <= swi(1); end RTL;