---------------------------------------------------------------------------- -- top.vhd (for axi3_test) -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- Vivado 2013.2: -- mkdir -p build.vivado -- (cd build.vivado; vivado -mode tcl -source ../vivado.tcl) -- (cd build.vivado; promgen -w -b -p bin -u 0 axi3_test.bit -data_width 32) -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.all; entity top is port ( clk_100_in : in std_logic; -- input clock to FPGA -- swi : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0) ); end entity top; architecture RTL of top is attribute DONT_TOUCH : string; -------------------------------------------------------------------- -- PS7 AXI Slave Signals -------------------------------------------------------------------- signal s_axi0_aclk : std_ulogic; signal s_axi0_areset_n : std_ulogic; signal s_axi0_arid : std_logic_vector(5 downto 0); signal s_axi0_araddr : std_logic_vector(31 downto 0); signal s_axi0_arburst : std_logic_vector(1 downto 0); signal s_axi0_arlen : std_logic_vector(3 downto 0); signal s_axi0_arsize : std_logic_vector(1 downto 0); signal s_axi0_arcache : std_logic_vector(3 downto 0); signal s_axi0_arvalid : std_ulogic; signal s_axi0_arready : std_ulogic; signal s_axi0_racount : std_logic_vector(2 downto 0); signal s_axi0_rid : std_logic_vector(5 downto 0); signal s_axi0_rdata : std_logic_vector(63 downto 0); signal s_axi0_rlast : std_ulogic; signal s_axi0_rresp : std_logic_vector(1 downto 0); signal s_axi0_rvalid : std_ulogic; signal s_axi0_rready : std_ulogic; signal s_axi0_rcount : std_logic_vector(7 downto 0); signal s_axi0_awid : std_logic_vector(5 downto 0); signal s_axi0_awaddr : std_logic_vector(31 downto 0); signal s_axi0_awburst : std_logic_vector(1 downto 0); signal s_axi0_awlen : std_logic_vector(3 downto 0); signal s_axi0_awsize : std_logic_vector(1 downto 0); signal s_axi0_awcache : std_logic_vector(3 downto 0); signal s_axi0_awvalid : std_ulogic; signal s_axi0_awready : std_ulogic; signal s_axi0_wacount : std_logic_vector(5 downto 0); signal s_axi0_wid : std_logic_vector(5 downto 0); signal s_axi0_wdata : std_logic_vector(63 downto 0); signal s_axi0_wstrb : std_logic_vector(7 downto 0); signal s_axi0_wlast : std_ulogic; signal s_axi0_wvalid : std_ulogic; signal s_axi0_wready : std_ulogic; signal s_axi0_wcount : std_logic_vector(7 downto 0); signal s_axi0_bid : std_logic_vector(5 downto 0); signal s_axi0_bresp : std_logic_vector(1 downto 0); signal s_axi0_bvalid : std_ulogic; signal s_axi0_bready : std_ulogic; -------------------------------------------------------------------- signal s_axi1_aclk : std_ulogic; signal s_axi1_areset_n : std_ulogic; signal s_axi1_arid : std_logic_vector(5 downto 0); signal s_axi1_araddr : std_logic_vector(31 downto 0); signal s_axi1_arburst : std_logic_vector(1 downto 0); signal s_axi1_arlen : std_logic_vector(3 downto 0); signal s_axi1_arsize : std_logic_vector(1 downto 0); signal s_axi1_arcache : std_logic_vector(3 downto 0); signal s_axi1_arvalid : std_ulogic; signal s_axi1_arready : std_ulogic; signal s_axi1_racount : std_logic_vector(2 downto 0); signal s_axi1_rid : std_logic_vector(5 downto 0); signal s_axi1_rdata : std_logic_vector(63 downto 0); signal s_axi1_rlast : std_ulogic; signal s_axi1_rresp : std_logic_vector(1 downto 0); signal s_axi1_rvalid : std_ulogic; signal s_axi1_rready : std_ulogic; signal s_axi1_rcount : std_logic_vector(7 downto 0); signal s_axi1_awid : std_logic_vector(5 downto 0); signal s_axi1_awaddr : std_logic_vector(31 downto 0); signal s_axi1_awburst : std_logic_vector(1 downto 0); signal s_axi1_awlen : std_logic_vector(3 downto 0); signal s_axi1_awsize : std_logic_vector(1 downto 0); signal s_axi1_awcache : std_logic_vector(3 downto 0); signal s_axi1_awvalid : std_ulogic; signal s_axi1_awready : std_ulogic; signal s_axi1_wacount : std_logic_vector(5 downto 0); signal s_axi1_wid : std_logic_vector(5 downto 0); signal s_axi1_wdata : std_logic_vector(63 downto 0); signal s_axi1_wstrb : std_logic_vector(7 downto 0); signal s_axi1_wlast : std_ulogic; signal s_axi1_wvalid : std_ulogic; signal s_axi1_wready : std_ulogic; signal s_axi1_wcount : std_logic_vector(7 downto 0); signal s_axi1_bid : std_logic_vector(5 downto 0); signal s_axi1_bresp : std_logic_vector(1 downto 0); signal s_axi1_bvalid : std_ulogic; signal s_axi1_bready : std_ulogic; -------------------------------------------------------------------- signal s_axi2_aclk : std_ulogic; signal s_axi2_areset_n : std_ulogic; signal s_axi2_arid : std_logic_vector(5 downto 0); signal s_axi2_araddr : std_logic_vector(31 downto 0); signal s_axi2_arburst : std_logic_vector(1 downto 0); signal s_axi2_arlen : std_logic_vector(3 downto 0); signal s_axi2_arsize : std_logic_vector(1 downto 0); signal s_axi2_arcache : std_logic_vector(3 downto 0); signal s_axi2_arvalid : std_ulogic; signal s_axi2_arready : std_ulogic; signal s_axi2_racount : std_logic_vector(2 downto 0); signal s_axi2_rid : std_logic_vector(5 downto 0); signal s_axi2_rdata : std_logic_vector(63 downto 0); signal s_axi2_rlast : std_ulogic; signal s_axi2_rresp : std_logic_vector(1 downto 0); signal s_axi2_rvalid : std_ulogic; signal s_axi2_rready : std_ulogic; signal s_axi2_rcount : std_logic_vector(7 downto 0); signal s_axi2_awid : std_logic_vector(5 downto 0); signal s_axi2_awaddr : std_logic_vector(31 downto 0); signal s_axi2_awburst : std_logic_vector(1 downto 0); signal s_axi2_awlen : std_logic_vector(3 downto 0); signal s_axi2_awsize : std_logic_vector(1 downto 0); signal s_axi2_awcache : std_logic_vector(3 downto 0); signal s_axi2_awvalid : std_ulogic; signal s_axi2_awready : std_ulogic; signal s_axi2_wacount : std_logic_vector(5 downto 0); signal s_axi2_wid : std_logic_vector(5 downto 0); signal s_axi2_wdata : std_logic_vector(63 downto 0); signal s_axi2_wstrb : std_logic_vector(7 downto 0); signal s_axi2_wlast : std_ulogic; signal s_axi2_wvalid : std_ulogic; signal s_axi2_wready : std_ulogic; signal s_axi2_wcount : std_logic_vector(7 downto 0); signal s_axi2_bid : std_logic_vector(5 downto 0); signal s_axi2_bresp : std_logic_vector(1 downto 0); signal s_axi2_bvalid : std_ulogic; signal s_axi2_bready : std_ulogic; -------------------------------------------------------------------- signal s_axi3_aclk : std_ulogic; signal s_axi3_areset_n : std_ulogic; signal s_axi3_arid : std_logic_vector(5 downto 0); signal s_axi3_araddr : std_logic_vector(31 downto 0); signal s_axi3_arburst : std_logic_vector(1 downto 0); signal s_axi3_arlen : std_logic_vector(3 downto 0); signal s_axi3_arsize : std_logic_vector(1 downto 0); signal s_axi3_arcache : std_logic_vector(3 downto 0); signal s_axi3_arvalid : std_ulogic; signal s_axi3_arready : std_ulogic; signal s_axi3_racount : std_logic_vector(2 downto 0); signal s_axi3_rid : std_logic_vector(5 downto 0); signal s_axi3_rdata : std_logic_vector(63 downto 0); signal s_axi3_rlast : std_ulogic; signal s_axi3_rresp : std_logic_vector(1 downto 0); signal s_axi3_rvalid : std_ulogic; signal s_axi3_rready : std_ulogic; signal s_axi3_rcount : std_logic_vector(7 downto 0); signal s_axi3_awid : std_logic_vector(5 downto 0); signal s_axi3_awaddr : std_logic_vector(31 downto 0); signal s_axi3_awburst : std_logic_vector(1 downto 0); signal s_axi3_awlen : std_logic_vector(3 downto 0); signal s_axi3_awsize : std_logic_vector(1 downto 0); signal s_axi3_awcache : std_logic_vector(3 downto 0); signal s_axi3_awvalid : std_ulogic; signal s_axi3_awready : std_ulogic; signal s_axi3_wacount : std_logic_vector(5 downto 0); signal s_axi3_wid : std_logic_vector(5 downto 0); signal s_axi3_wdata : std_logic_vector(63 downto 0); signal s_axi3_wstrb : std_logic_vector(7 downto 0); signal s_axi3_wlast : std_ulogic; signal s_axi3_wvalid : std_ulogic; signal s_axi3_wready : std_ulogic; signal s_axi3_wcount : std_logic_vector(7 downto 0); signal s_axi3_bid : std_logic_vector(5 downto 0); signal s_axi3_bresp : std_logic_vector(1 downto 0); signal s_axi3_bvalid : std_ulogic; signal s_axi3_bready : std_ulogic; -------------------------------------------------------------------- -- Clock Signals -------------------------------------------------------------------- signal clk_100 : std_ulogic; attribute dont_touch of clk_100 : signal is "true"; -------------------------------------------------------------------- -- AXI MMCM Signals -------------------------------------------------------------------- signal axi_mmcm_reset_n : std_ulogic; signal axi_mmcm : std_logic_vector(6 downto 0); signal axi_mmcm_locked : std_ulogic; signal axi0_clk_150 : std_ulogic; signal axi1_clk_150 : std_ulogic; signal axi2_clk_150 : std_ulogic; signal axi3_clk_150 : std_ulogic; signal axi0_clk_100 : std_ulogic; signal axi1_clk_100 : std_ulogic; attribute dont_touch of axi_mmcm : signal is "true"; -------------------------------------------------------------------- -- Writer Signals -------------------------------------------------------------------- signal data0_clk : std_ulogic; signal data0_enable : std_ulogic; signal data0_in : std_logic_vector(63 downto 0); signal data0_full : std_ulogic; signal data0_reset_n : std_ulogic; signal addr0_clk : std_ulogic; signal addr0_enable : std_ulogic; signal addr0_in : std_logic_vector(31 downto 0); signal addr0_full : std_ulogic; signal addr0_reset_n : std_ulogic; signal writer0_state : std_logic_vector(7 downto 0); signal data1_clk : std_ulogic; signal data1_enable : std_ulogic; signal data1_in : std_logic_vector(63 downto 0); signal data1_full : std_ulogic; signal data1_reset_n : std_ulogic; signal addr1_clk : std_ulogic; signal addr1_enable : std_ulogic; signal addr1_in : std_logic_vector(31 downto 0); signal addr1_full : std_ulogic; signal addr1_reset_n : std_ulogic; signal writer1_state : std_logic_vector(7 downto 0); signal data2_clk : std_ulogic; signal data2_enable : std_ulogic; signal data2_in : std_logic_vector(63 downto 0); signal data2_full : std_ulogic; signal data2_reset_n : std_ulogic; signal addr2_clk : std_ulogic; signal addr2_enable : std_ulogic; signal addr2_in : std_logic_vector(31 downto 0); signal addr2_full : std_ulogic; signal addr2_reset_n : std_ulogic; signal writer2_state : std_logic_vector(7 downto 0); signal data3_clk : std_ulogic; signal data3_enable : std_ulogic; signal data3_in : std_logic_vector(63 downto 0); signal data3_full : std_ulogic; signal data3_reset_n : std_ulogic; signal addr3_clk : std_ulogic; signal addr3_enable : std_ulogic; signal addr3_in : std_logic_vector(31 downto 0); signal addr3_full : std_ulogic; signal addr3_reset_n : std_ulogic; signal writer3_state : std_logic_vector(7 downto 0); begin -------------------------------------------------------------------- -- PS7 Interface -------------------------------------------------------------------- ps7_stub_inst : entity work.ps7_stub port map ( s_axi0_aclk => s_axi0_aclk, s_axi0_areset_n => s_axi0_areset_n, -- s_axi0_arid => s_axi0_arid, s_axi0_araddr => s_axi0_araddr, s_axi0_arburst => s_axi0_arburst, s_axi0_arlen => s_axi0_arlen, s_axi0_arsize => s_axi0_arsize, s_axi0_arcache => s_axi0_arcache, s_axi0_arvalid => s_axi0_arvalid, s_axi0_arready => s_axi0_arready, s_axi0_racount => s_axi0_racount, -- s_axi0_rid => s_axi0_rid, s_axi0_rdata => s_axi0_rdata, s_axi0_rlast => s_axi0_rlast, s_axi0_rresp => s_axi0_rresp, s_axi0_rvalid => s_axi0_rvalid, s_axi0_rready => s_axi0_rready, s_axi0_rcount => s_axi0_rcount, -- s_axi0_awid => s_axi0_awid, s_axi0_awaddr => s_axi0_awaddr, s_axi0_awburst => s_axi0_awburst, s_axi0_awlen => s_axi0_awlen, s_axi0_awsize => s_axi0_awsize, s_axi0_awcache => s_axi0_awcache, s_axi0_awvalid => s_axi0_awvalid, s_axi0_awready => s_axi0_awready, s_axi0_wacount => s_axi0_wacount, -- s_axi0_wid => s_axi0_wid, s_axi0_wdata => s_axi0_wdata, s_axi0_wstrb => s_axi0_wstrb, s_axi0_wlast => s_axi0_wlast, s_axi0_wvalid => s_axi0_wvalid, s_axi0_wready => s_axi0_wready, s_axi0_wcount => s_axi0_wcount, -- s_axi0_bid => s_axi0_bid, s_axi0_bresp => s_axi0_bresp, s_axi0_bvalid => s_axi0_bvalid, s_axi0_bready => s_axi0_bready, -- s_axi1_aclk => s_axi1_aclk, s_axi1_areset_n => s_axi1_areset_n, -- s_axi1_arid => s_axi1_arid, s_axi1_araddr => s_axi1_araddr, s_axi1_arburst => s_axi1_arburst, s_axi1_arlen => s_axi1_arlen, s_axi1_arsize => s_axi1_arsize, s_axi1_arcache => s_axi1_arcache, s_axi1_arvalid => s_axi1_arvalid, s_axi1_arready => s_axi1_arready, s_axi1_racount => s_axi1_racount, -- s_axi1_rid => s_axi1_rid, s_axi1_rdata => s_axi1_rdata, s_axi1_rlast => s_axi1_rlast, s_axi1_rresp => s_axi1_rresp, s_axi1_rvalid => s_axi1_rvalid, s_axi1_rready => s_axi1_rready, s_axi1_rcount => s_axi1_rcount, -- s_axi1_awid => s_axi1_awid, s_axi1_awaddr => s_axi1_awaddr, s_axi1_awburst => s_axi1_awburst, s_axi1_awlen => s_axi1_awlen, s_axi1_awsize => s_axi1_awsize, s_axi1_awcache => s_axi1_awcache, s_axi1_awvalid => s_axi1_awvalid, s_axi1_awready => s_axi1_awready, s_axi1_wacount => s_axi1_wacount, -- s_axi1_wid => s_axi1_wid, s_axi1_wdata => s_axi1_wdata, s_axi1_wstrb => s_axi1_wstrb, s_axi1_wlast => s_axi1_wlast, s_axi1_wvalid => s_axi1_wvalid, s_axi1_wready => s_axi1_wready, s_axi1_wcount => s_axi1_wcount, -- s_axi1_bid => s_axi1_bid, s_axi1_bresp => s_axi1_bresp, s_axi1_bvalid => s_axi1_bvalid, s_axi1_bready => s_axi1_bready, -- s_axi2_aclk => s_axi2_aclk, s_axi2_areset_n => s_axi2_areset_n, -- s_axi2_arid => s_axi2_arid, s_axi2_araddr => s_axi2_araddr, s_axi2_arburst => s_axi2_arburst, s_axi2_arlen => s_axi2_arlen, s_axi2_arsize => s_axi2_arsize, s_axi2_arcache => s_axi2_arcache, s_axi2_arvalid => s_axi2_arvalid, s_axi2_arready => s_axi2_arready, s_axi2_racount => s_axi2_racount, -- s_axi2_rid => s_axi2_rid, s_axi2_rdata => s_axi2_rdata, s_axi2_rlast => s_axi2_rlast, s_axi2_rresp => s_axi2_rresp, s_axi2_rvalid => s_axi2_rvalid, s_axi2_rready => s_axi2_rready, s_axi2_rcount => s_axi2_rcount, -- s_axi2_awid => s_axi2_awid, s_axi2_awaddr => s_axi2_awaddr, s_axi2_awburst => s_axi2_awburst, s_axi2_awlen => s_axi2_awlen, s_axi2_awsize => s_axi2_awsize, s_axi2_awcache => s_axi2_awcache, s_axi2_awvalid => s_axi2_awvalid, s_axi2_awready => s_axi2_awready, s_axi2_wacount => s_axi2_wacount, -- s_axi2_wid => s_axi2_wid, s_axi2_wdata => s_axi2_wdata, s_axi2_wstrb => s_axi2_wstrb, s_axi2_wlast => s_axi2_wlast, s_axi2_wvalid => s_axi2_wvalid, s_axi2_wready => s_axi2_wready, s_axi2_wcount => s_axi2_wcount, -- s_axi2_bid => s_axi2_bid, s_axi2_bresp => s_axi2_bresp, s_axi2_bvalid => s_axi2_bvalid, s_axi2_bready => s_axi2_bready, -- s_axi3_aclk => s_axi3_aclk, s_axi3_areset_n => s_axi3_areset_n, -- s_axi3_arid => s_axi3_arid, s_axi3_araddr => s_axi3_araddr, s_axi3_arburst => s_axi3_arburst, s_axi3_arlen => s_axi3_arlen, s_axi3_arsize => s_axi3_arsize, s_axi3_arcache => s_axi3_arcache, s_axi3_arvalid => s_axi3_arvalid, s_axi3_arready => s_axi3_arready, s_axi3_racount => s_axi3_racount, -- s_axi3_rid => s_axi3_rid, s_axi3_rdata => s_axi3_rdata, s_axi3_rlast => s_axi3_rlast, s_axi3_rresp => s_axi3_rresp, s_axi3_rvalid => s_axi3_rvalid, s_axi3_rready => s_axi3_rready, s_axi3_rcount => s_axi3_rcount, -- s_axi3_awid => s_axi3_awid, s_axi3_awaddr => s_axi3_awaddr, s_axi3_awburst => s_axi3_awburst, s_axi3_awlen => s_axi3_awlen, s_axi3_awsize => s_axi3_awsize, s_axi3_awcache => s_axi3_awcache, s_axi3_awvalid => s_axi3_awvalid, s_axi3_awready => s_axi3_awready, s_axi3_wacount => s_axi3_wacount, -- s_axi3_wid => s_axi3_wid, s_axi3_wdata => s_axi3_wdata, s_axi3_wstrb => s_axi3_wstrb, s_axi3_wlast => s_axi3_wlast, s_axi3_wvalid => s_axi3_wvalid, s_axi3_wready => s_axi3_wready, s_axi3_wcount => s_axi3_wcount, -- s_axi3_bid => s_axi3_bid, s_axi3_bresp => s_axi3_bresp, s_axi3_bvalid => s_axi3_bvalid, s_axi3_bready => s_axi3_bready ); -------------------------------------------------------------------- -- Clock Buffer -------------------------------------------------------------------- BUFGP_inst : BUFGP port map ( O => clk_100, I => clk_100_in ); -------------------------------------------------------------------- -- AXI MMCM -------------------------------------------------------------------- axi_mmcm_inst : entity work.axi_mmcm port map ( clk_in => clk_100, reset_n => axi_mmcm_reset_n, -- mmcm_clk => axi_mmcm, -- mmcm_locked => axi_mmcm_locked ); axi0_clk_150 <= axi_mmcm(0); axi1_clk_150 <= axi_mmcm(1); axi2_clk_150 <= axi_mmcm(2); axi3_clk_150 <= axi_mmcm(3); axi0_clk_100 <= axi_mmcm(4); axi1_clk_100 <= axi_mmcm(5); axi_mmcm_reset_n <= swi(1); -------------------------------------------------------------------- -- LED Status output -------------------------------------------------------------------- led(0) <= axi_mmcm_locked; led(1) <= '0'; led(3 downto 2) <= swi(3 downto 2); led(4) <= data0_full; led(5) <= data1_full; led(6) <= data2_full; led(7) <= data3_full; -------------------------------------------------------------------- -- AXIHP Writer 0 -------------------------------------------------------------------- axihp_writer_inst0 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, AWID_MASK => "001111", AWID_DATA => "000000" ) port map ( s_axi_aclk => s_axi0_aclk, s_axi_areset_n => s_axi0_areset_n, enable => swi(4), -- s_axi_awid => s_axi0_awid, s_axi_awaddr => s_axi0_awaddr, s_axi_awburst => s_axi0_awburst, s_axi_awlen => s_axi0_awlen, s_axi_awsize => s_axi0_awsize, s_axi_awcache => s_axi0_awcache, s_axi_awvalid => s_axi0_awvalid, s_axi_awready => s_axi0_awready, s_axi_wacount => s_axi0_wacount, -- s_axi_wid => s_axi0_wid, s_axi_wdata => s_axi0_wdata, s_axi_wstrb => s_axi0_wstrb, s_axi_wlast => s_axi0_wlast, s_axi_wvalid => s_axi0_wvalid, s_axi_wready => s_axi0_wready, s_axi_wcount => s_axi0_wcount, -- s_axi_bid => s_axi0_bid, s_axi_bresp => s_axi0_bresp, s_axi_bvalid => s_axi0_bvalid, s_axi_bready => s_axi0_bready, -- data_clk => data0_clk, data_enable => data0_enable, data_in => data0_in, data_full => data0_full, -- addr_clk => addr0_clk, addr_enable => addr0_enable, addr_in => addr0_in, addr_full => addr0_full, -- writer_state => writer0_state ); s_axi0_aclk <= axi0_clk_150; data_gen_inst0 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data0_clk, reset_n => data0_reset_n, enable => data0_enable, -- data_min => x"00000000", data_inc => x"00000001", data_max => x"0FFFFFFF", -- data => data0_in(31 downto 0) ); data0_in(63 downto 32) <= x"00000000"; data0_clk <= axi0_clk_150; data0_enable <= not data0_full; data0_reset_n <= swi(0); addr_gen_inst0 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr0_clk, reset_n => addr0_reset_n, enable => addr0_enable, -- data_min => x"1B000000", data_inc => x"00000080", data_max => x"1B0FFF80", -- data => addr0_in ); addr0_clk <= axi0_clk_100; addr0_enable <= not addr0_full; addr0_reset_n <= swi(0); s_axi0_arid <= (others => '0'); s_axi0_araddr <= (others => '0'); s_axi0_arburst <= (others => '0'); s_axi0_arlen <= (others => '0'); s_axi0_arsize <= (others => '0'); s_axi0_arcache <= (others => '0'); s_axi0_arvalid <= '0'; s_axi0_rready <= '0'; -------------------------------------------------------------------- -- AXIHP Writer 1 -------------------------------------------------------------------- axihp_writer_inst1 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, AWID_MASK => "001111", AWID_DATA => "010000" ) port map ( s_axi_aclk => s_axi1_aclk, s_axi_areset_n => s_axi1_areset_n, enable => swi(5), -- s_axi_awid => s_axi1_awid, s_axi_awaddr => s_axi1_awaddr, s_axi_awburst => s_axi1_awburst, s_axi_awlen => s_axi1_awlen, s_axi_awsize => s_axi1_awsize, s_axi_awcache => s_axi1_awcache, s_axi_awvalid => s_axi1_awvalid, s_axi_awready => s_axi1_awready, s_axi_wacount => s_axi1_wacount, -- s_axi_wid => s_axi1_wid, s_axi_wdata => s_axi1_wdata, s_axi_wstrb => s_axi1_wstrb, s_axi_wlast => s_axi1_wlast, s_axi_wvalid => s_axi1_wvalid, s_axi_wready => s_axi1_wready, s_axi_wcount => s_axi1_wcount, -- s_axi_bid => s_axi1_bid, s_axi_bresp => s_axi1_bresp, s_axi_bvalid => s_axi1_bvalid, s_axi_bready => s_axi1_bready, -- data_clk => data1_clk, data_enable => data1_enable, data_in => data1_in, data_full => data1_full, -- addr_clk => addr1_clk, addr_enable => addr1_enable, addr_in => addr1_in, addr_full => addr1_full, -- writer_state => writer1_state ); s_axi1_aclk <= axi1_clk_150; data_gen_inst1 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data1_clk, reset_n => data1_reset_n, enable => data1_enable, -- data_min => x"20000000", data_inc => x"00000001", data_max => x"2FFFFFFF", -- data => data1_in(31 downto 0) ); data1_in(63 downto 32) <= x"11111111"; data1_clk <= axi1_clk_150; data1_enable <= not data1_full; data1_reset_n <= swi(0); addr_gen_inst1 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr1_clk, reset_n => addr1_reset_n, enable => addr1_enable, -- data_min => x"1B200000", data_inc => x"00000080", data_max => x"1B2FFF80", -- data => addr1_in ); addr1_clk <= axi0_clk_100; addr1_enable <= not addr1_full; addr1_reset_n <= swi(0); s_axi1_arid <= (others => '0'); s_axi1_araddr <= (others => '0'); s_axi1_arburst <= (others => '0'); s_axi1_arlen <= (others => '0'); s_axi1_arsize <= (others => '0'); s_axi1_arcache <= (others => '0'); s_axi1_arvalid <= '0'; s_axi1_rready <= '0'; -------------------------------------------------------------------- -- AXIHP Writer 2 -------------------------------------------------------------------- axihp_writer_inst2 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, AWID_MASK => "001111", AWID_DATA => "101111" ) port map ( s_axi_aclk => s_axi2_aclk, s_axi_areset_n => s_axi2_areset_n, enable => swi(6), -- s_axi_awid => s_axi2_awid, s_axi_awaddr => s_axi2_awaddr, s_axi_awburst => s_axi2_awburst, s_axi_awlen => s_axi2_awlen, s_axi_awsize => s_axi2_awsize, s_axi_awcache => s_axi2_awcache, s_axi_awvalid => s_axi2_awvalid, s_axi_awready => s_axi2_awready, s_axi_wacount => s_axi2_wacount, -- s_axi_wid => s_axi2_wid, s_axi_wdata => s_axi2_wdata, s_axi_wstrb => s_axi2_wstrb, s_axi_wlast => s_axi2_wlast, s_axi_wvalid => s_axi2_wvalid, s_axi_wready => s_axi2_wready, s_axi_wcount => s_axi2_wcount, -- s_axi_bid => s_axi2_bid, s_axi_bresp => s_axi2_bresp, s_axi_bvalid => s_axi2_bvalid, s_axi_bready => s_axi2_bready, -- data_clk => data2_clk, data_enable => data2_enable, data_in => data2_in, data_full => data2_full, -- addr_clk => addr2_clk, addr_enable => addr2_enable, addr_in => addr2_in, addr_full => addr2_full, -- writer_state => writer2_state ); s_axi2_aclk <= axi2_clk_150; data_gen_inst2 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data2_clk, reset_n => data2_reset_n, enable => data2_enable, -- data_min => x"40000000", data_inc => x"00000001", data_max => x"4FFFFFFF", -- data => data2_in(31 downto 0) ); data2_in(63 downto 32) <= x"22222222"; data2_clk <= axi2_clk_150; data2_enable <= not data2_full; data2_reset_n <= swi(0); addr_gen_inst2 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr2_clk, reset_n => addr2_reset_n, enable => addr2_enable, -- data_min => x"1B400000", data_inc => x"00000080", data_max => x"1B4FFF80", -- data => addr2_in ); addr2_clk <= axi0_clk_100; addr2_enable <= not addr2_full; addr2_reset_n <= swi(0); s_axi2_arid <= (others => '0'); s_axi2_araddr <= (others => '0'); s_axi2_arburst <= (others => '0'); s_axi2_arlen <= (others => '0'); s_axi2_arsize <= (others => '0'); s_axi2_arcache <= (others => '0'); s_axi2_arvalid <= '0'; s_axi2_rready <= '0'; -------------------------------------------------------------------- -- AXIHP Writer 3 -------------------------------------------------------------------- axihp_writer_inst3 : entity work.axihp_writer generic map ( DATA_WIDTH => 64, DATA_COUNT => 16, AWID_MASK => "001111", AWID_DATA => "110000" ) port map ( s_axi_aclk => s_axi3_aclk, s_axi_areset_n => s_axi3_areset_n, enable => swi(7), -- s_axi_awid => s_axi3_awid, s_axi_awaddr => s_axi3_awaddr, s_axi_awburst => s_axi3_awburst, s_axi_awlen => s_axi3_awlen, s_axi_awsize => s_axi3_awsize, s_axi_awcache => s_axi3_awcache, s_axi_awvalid => s_axi3_awvalid, s_axi_awready => s_axi3_awready, s_axi_wacount => s_axi3_wacount, -- s_axi_wid => s_axi3_wid, s_axi_wdata => s_axi3_wdata, s_axi_wstrb => s_axi3_wstrb, s_axi_wlast => s_axi3_wlast, s_axi_wvalid => s_axi3_wvalid, s_axi_wready => s_axi3_wready, s_axi_wcount => s_axi3_wcount, -- s_axi_bid => s_axi3_bid, s_axi_bresp => s_axi3_bresp, s_axi_bvalid => s_axi3_bvalid, s_axi_bready => s_axi3_bready, -- data_clk => data3_clk, data_enable => data3_enable, data_in => data3_in, data_full => data3_full, -- addr_clk => addr3_clk, addr_enable => addr3_enable, addr_in => addr3_in, addr_full => addr3_full, -- writer_state => writer3_state ); s_axi3_aclk <= axi3_clk_150; data_gen_inst3 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => data3_clk, reset_n => data3_reset_n, enable => data3_enable, -- data_min => x"60000000", data_inc => x"00000001", data_max => x"6FFFFFFF", -- data => data3_in(31 downto 0) ); data3_in(63 downto 32) <= x"33333333"; data3_clk <= axi3_clk_150; data3_enable <= not data3_full; data3_reset_n <= swi(0); addr_gen_inst3 : entity work.data_gen generic map ( DATA_WIDTH => 32 ) port map ( clk => addr3_clk, reset_n => addr3_reset_n, enable => addr3_enable, -- data_min => x"1B600000", data_inc => x"00000080", data_max => x"1B6FFF80", -- data => addr3_in ); addr3_clk <= axi0_clk_100; addr3_enable <= not addr3_full; addr3_reset_n <= swi(0); s_axi3_arid <= (others => '0'); s_axi3_araddr <= (others => '0'); s_axi3_arburst <= (others => '0'); s_axi3_arlen <= (others => '0'); s_axi3_arsize <= (others => '0'); s_axi3_arcache <= (others => '0'); s_axi3_arvalid <= '0'; s_axi3_rready <= '0'; end RTL;