----------------------------------------------------------------------------
--  ps7_stub.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity ps7_stub is
    port (
	ddr_addr	: inout std_logic_vector(14 downto 0)	:= (others => '0');
	ddr_bankaddr	: inout std_logic_vector(2 downto 0)	:= (others => '0');
	ddr_cas_n	: inout std_ulogic			:= '0';
	ddr_cke		: inout std_ulogic			:= '0';
	ddr_clk		: inout std_ulogic			:= '0';
	ddr_clk_n	: inout std_ulogic			:= '0';
	ddr_cs_n	: inout std_ulogic			:= '0';
	ddr_dm		: inout std_logic_vector(3 downto 0)	:= (others => '0');
	ddr_dq		: inout std_logic_vector(31 downto 0)	:= (others => '0');
	ddr_dqs		: inout std_logic_vector(3 downto 0)	:= (others => '0');
	ddr_dqs_n	: inout std_logic_vector(3 downto 0)	:= (others => '0');
	ddr_drstb	: inout std_ulogic			:= '0';
	ddr_odt		: inout std_ulogic			:= '0';
	ddr_ras_n	: inout std_ulogic			:= '0';
	ddr_vr_n	: inout std_ulogic			:= '0';
	ddr_vr		: inout std_ulogic			:= '0';
	ddr_web		: inout std_ulogic			:= '0';
	--
	ps_mio		: inout std_logic_vector(53 downto 0);
	--
	ps_clk		: inout std_ulogic			:= '0';
	ps_porb		: inout std_ulogic			:= '0';
	ps_srstb	: inout std_ulogic			:= '0';
	--
	ps_fclk		: out std_logic_vector(3 downto 0);
	--
	emio_gpio_i	: in std_logic_vector(63 downto 0)	:= (others => '0');
	emio_gpio_o	: out std_logic_vector(63 downto 0);
	emio_gpio_t_n	: out std_logic_vector(63 downto 0);
	--
	i2c0_sda_i	: in std_ulogic				:= '0';
	i2c0_sda_o	: out std_ulogic;
	i2c0_sda_t_n	: out std_ulogic;
	--
	i2c0_scl_i	: in std_ulogic				:= '0';
	i2c0_scl_o	: out std_ulogic;
	i2c0_scl_t_n	: out std_ulogic;
	--
	i2c1_sda_i	: in std_ulogic				:= '0';
	i2c1_sda_o	: out std_ulogic;
	i2c1_sda_t_n	: out std_ulogic;
	--
	i2c1_scl_i	: in std_ulogic				:= '0';
	i2c1_scl_o	: out std_ulogic;
	i2c1_scl_t_n	: out std_ulogic;
	--
	m_axi0_aclk	: in std_ulogic				:= '0';
	m_axi0_areset_n	: out std_ulogic;
	--	read address
	m_axi0_arid	: out std_logic_vector(11 downto 0);
	m_axi0_araddr	: out std_logic_vector(31 downto 0);
	m_axi0_arburst	: out std_logic_vector(1 downto 0);
	m_axi0_arlen	: out std_logic_vector(3 downto 0);
	m_axi0_arsize	: out std_logic_vector(1 downto 0);
	m_axi0_arvalid	: out std_ulogic;
	m_axi0_arready	: in std_ulogic				:= '0';
	--	read data
	m_axi0_rid	: in std_logic_vector(11 downto 0)	:= (others => '0');
	m_axi0_rdata	: in std_logic_vector(31 downto 0)	:= (others => '0');
	m_axi0_rlast	: in std_ulogic				:= '1';
	m_axi0_rresp	: in std_logic_vector(1 downto 0)	:= (others => '0');
	m_axi0_rvalid	: in std_ulogic				:= '0';
	m_axi0_rready	: out std_ulogic;
	--	write address
	m_axi0_awid	: out std_logic_vector(11 downto 0);
	m_axi0_awaddr	: out std_logic_vector(31 downto 0);
	m_axi0_awburst	: out std_logic_vector(1 downto 0);
	m_axi0_awlen	: out std_logic_vector(3 downto 0);
	m_axi0_awsize	: out std_logic_vector(1 downto 0);
	m_axi0_awvalid	: out std_ulogic;
	m_axi0_awready	: in std_ulogic				:= '0';
	--	write data
	m_axi0_wid	: out std_logic_vector(11 downto 0);
	m_axi0_wdata	: out std_logic_vector(31 downto 0);
	m_axi0_wstrb	: out std_logic_vector(3 downto 0);
	m_axi0_wlast	: out std_ulogic;
	m_axi0_wvalid	: out std_ulogic;
	m_axi0_wready	: in std_ulogic				:= '0';
	--	write response
	m_axi0_bid	: in std_logic_vector(11 downto 0)	:= (others => '0');
	m_axi0_bresp	: in std_logic_vector(1 downto 0)	:= (others => '0');
	m_axi0_bvalid	: in std_ulogic				:= '0';
	m_axi0_bready	: out std_ulogic;
	--
	m_axi1_aclk	: in std_ulogic				:= '0';
	m_axi1_areset_n	: out std_ulogic;
	--	read address
	m_axi1_arid	: out std_logic_vector(11 downto 0);
	m_axi1_araddr	: out std_logic_vector(31 downto 0);
	m_axi1_arburst	: out std_logic_vector(1 downto 0);
	m_axi1_arlen	: out std_logic_vector(3 downto 0);
	m_axi1_arsize	: out std_logic_vector(1 downto 0);
	m_axi1_arvalid	: out std_logic;
	m_axi1_arready	: in std_ulogic				:= '0';
	--	read data
	m_axi1_rid	: in std_logic_vector(11 downto 0)	:= (others => '0');
	m_axi1_rdata	: in std_logic_vector(31 downto 0)	:= (others => '0');
	m_axi1_rlast	: in std_ulogic				:= '1';
	m_axi1_rresp	: in std_logic_vector(1 downto 0)	:= (others => '0');
	m_axi1_rvalid	: in std_ulogic				:= '0';
	m_axi1_rready	: out std_ulogic;
	--	write address
	m_axi1_awid	: out std_logic_vector(11 downto 0);
	m_axi1_awaddr	: out std_logic_vector(31 downto 0);
	m_axi1_awburst	: out std_logic_vector(1 downto 0);
	m_axi1_awlen	: out std_logic_vector(3 downto 0);
	m_axi1_awsize	: out std_logic_vector(1 downto 0);
	m_axi1_awvalid	: out std_ulogic;
	m_axi1_awready	: in std_ulogic				:= '0';
	--	write data
	m_axi1_wid	: out std_logic_vector(11 downto 0);
	m_axi1_wdata	: out std_logic_vector(31 downto 0);
	m_axi1_wstrb	: out std_logic_vector(3 downto 0);
	m_axi1_wlast	: out std_ulogic;
	m_axi1_wvalid	: out std_ulogic;
	m_axi1_wready	: in std_ulogic				:= '0';
	--	write response
	m_axi1_bid	: in std_logic_vector(11 downto 0)	:= (others => '0');
	m_axi1_bresp	: in std_logic_vector(1 downto 0)	:= (others => '0');
	m_axi1_bvalid	: in std_ulogic				:= '0';
	m_axi1_bready	: out std_ulogic;
	--
	s_axi0_aclk	: in std_ulogic				:= '0';
	s_axi0_areset_n	: out std_ulogic;
	--	read address
	s_axi0_arid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi0_araddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi0_arburst	: in std_logic_vector(1 downto 0)	:= "01";
	s_axi0_arlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi0_arsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi0_arcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi0_arvalid	: in std_ulogic				:= '0';
	s_axi0_arready	: out std_ulogic;
	s_axi0_racount	: out std_logic_vector(2 downto 0);
	--	read data
	s_axi0_rid	: out std_logic_vector(5 downto 0);
	s_axi0_rdata	: out std_logic_vector(63 downto 0);
	s_axi0_rlast	: out std_ulogic;
	s_axi0_rresp	: out std_logic_vector(1 downto 0);
	s_axi0_rvalid	: out std_ulogic;
	s_axi0_rready	: in std_ulogic				:= '0';
	s_axi0_rcount	: out std_logic_vector(7 downto 0);
	--	write address
	s_axi0_awid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi0_awaddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi0_awburst	: in std_logic_vector(1 downto 0)	:= "01";
	s_axi0_awlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi0_awsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi0_awcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi0_awvalid	: in std_ulogic				:= '0';
	s_axi0_awready	: out std_ulogic;
	s_axi0_wacount	: out std_logic_vector(5 downto 0);
	--	write data
	s_axi0_wid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi0_wdata	: in std_logic_vector(63 downto 0)	:= (others => '0');
	s_axi0_wstrb	: in std_logic_vector(7 downto 0)	:= (others => '0');
	s_axi0_wlast	: in std_ulogic				:= '0';
	s_axi0_wvalid	: in std_ulogic				:= '0';
	s_axi0_wready	: out std_ulogic			:= '0';
	s_axi0_wcount	: out std_logic_vector(7 downto 0);
	--	write response
	s_axi0_bid	: out std_logic_vector(5 downto 0);
	s_axi0_bresp	: out std_logic_vector(1 downto 0);
	s_axi0_bvalid	: out std_ulogic;
	s_axi0_bready	: in std_ulogic				:= '0';
	--
	s_axi1_aclk	: in std_ulogic				:= '0';
	s_axi1_areset_n	: out std_ulogic;
	--	read address
	s_axi1_arid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi1_araddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi1_arburst	: in std_logic_vector(1 downto 0)	:= "01";
	s_axi1_arlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi1_arsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi1_arcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi1_arvalid	: in std_ulogic				:= '0';
	s_axi1_arready	: out std_ulogic;
	s_axi1_racount	: out std_logic_vector(2 downto 0);
	--	read data
	s_axi1_rid	: out std_logic_vector(5 downto 0);
	s_axi1_rdata	: out std_logic_vector(63 downto 0);
	s_axi1_rlast	: out std_ulogic;
	s_axi1_rresp	: out std_logic_vector(1 downto 0);
	s_axi1_rvalid	: out std_ulogic;
	s_axi1_rready	: in std_ulogic				:= '0';
	s_axi1_rcount	: out std_logic_vector(7 downto 0);
	--	write address
	s_axi1_awid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi1_awaddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi1_awburst	: in std_logic_vector(1 downto 0)	:= "01";
	s_axi1_awlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi1_awsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi1_awcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi1_awvalid	: in std_ulogic				:= '0';
	s_axi1_awready	: out std_ulogic;
	s_axi1_wacount	: out std_logic_vector(5 downto 0);
	--	write data
	s_axi1_wid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi1_wdata	: in std_logic_vector(63 downto 0)	:= (others => '0');
	s_axi1_wstrb	: in std_logic_vector(7 downto 0)	:= (others => '0');
	s_axi1_wlast	: in std_ulogic				:= '0';
	s_axi1_wvalid	: in std_ulogic				:= '0';
	s_axi1_wready	: out std_ulogic			:= '0';
	s_axi1_wcount	: out std_logic_vector(7 downto 0);
	--	write response
	s_axi1_bid	: out std_logic_vector(5 downto 0);
	s_axi1_bresp	: out std_logic_vector(1 downto 0);
	s_axi1_bvalid	: out std_ulogic;
	s_axi1_bready	: in std_ulogic				:= '0';
	--
	s_axi2_aclk	: in std_ulogic				:= '0';
	s_axi2_areset_n	: out std_ulogic;
	--	read address
	s_axi2_arid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi2_araddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi2_arburst	: in std_logic_vector(1 downto 0)	:= "01";
	s_axi2_arlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi2_arsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi2_arcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi2_arvalid	: in std_ulogic				:= '0';
	s_axi2_arready	: out std_ulogic;
	s_axi2_racount	: out std_logic_vector(2 downto 0);
	--	read data
	s_axi2_rid	: out std_logic_vector(5 downto 0);
	s_axi2_rdata	: out std_logic_vector(63 downto 0);
	s_axi2_rlast	: out std_ulogic;
	s_axi2_rresp	: out std_logic_vector(1 downto 0);
	s_axi2_rvalid	: out std_ulogic;
	s_axi2_rready	: in std_ulogic				:= '0';
	s_axi2_rcount	: out std_logic_vector(7 downto 0);
	--	write address
	s_axi2_awid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi2_awaddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi2_awburst	: in std_logic_vector(1 downto 0)	:= (others => '0');
	s_axi2_awlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi2_awsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi2_awcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi2_awvalid	: in std_ulogic				:= '0';
	s_axi2_awready	: out std_ulogic;
	s_axi2_wacount	: out std_logic_vector(5 downto 0);
	--	write data
	s_axi2_wid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi2_wdata	: in std_logic_vector(63 downto 0)	:= (others => '0');
	s_axi2_wstrb	: in std_logic_vector(7 downto 0)	:= (others => '0');
	s_axi2_wlast	: in std_ulogic				:= '0';
	s_axi2_wvalid	: in std_ulogic				:= '0';
	s_axi2_wready	: out std_ulogic			:= '0';
	s_axi2_wcount	: out std_logic_vector(7 downto 0);
	--	write response
	s_axi2_bid	: out std_logic_vector(5 downto 0);
	s_axi2_bresp	: out std_logic_vector(1 downto 0);
	s_axi2_bvalid	: out std_ulogic;
	s_axi2_bready	: in std_ulogic				:= '0';
	--
	s_axi3_aclk	: in std_ulogic				:= '0';
	s_axi3_areset_n	: out std_ulogic;
	--	read address
	s_axi3_arid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi3_araddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi3_arburst	: in std_logic_vector(1 downto 0)	:= (others => '0');
	s_axi3_arlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi3_arsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi3_arcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi3_arvalid	: in std_ulogic				:= '0';
	s_axi3_arready	: out std_ulogic;
	s_axi3_racount	: out std_logic_vector(2 downto 0);
	--	read data
	s_axi3_rid	: out std_logic_vector(5 downto 0);
	s_axi3_rdata	: out std_logic_vector(63 downto 0);
	s_axi3_rlast	: out std_ulogic;
	s_axi3_rresp	: out std_logic_vector(1 downto 0);
	s_axi3_rvalid	: out std_ulogic;
	s_axi3_rready	: in std_ulogic				:= '0';
	s_axi3_rcount	: out std_logic_vector(7 downto 0);
	--	write address
	s_axi3_awid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi3_awaddr	: in std_logic_vector(31 downto 0)	:= (others => '0');
	s_axi3_awburst	: in std_logic_vector(1 downto 0)	:= (others => '0');
	s_axi3_awlen	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi3_awsize	: in std_logic_vector(1 downto 0)	:= "11";
	s_axi3_awcache	: in std_logic_vector(3 downto 0)	:= (others => '0');
	s_axi3_awvalid	: in std_ulogic				:= '0';
	s_axi3_awready	: out std_ulogic;
	s_axi3_wacount	: out std_logic_vector(5 downto 0);
	--	write data
	s_axi3_wid	: in std_logic_vector(5 downto 0)	:= (others => '0');
	s_axi3_wdata	: in std_logic_vector(63 downto 0)	:= (others => '0');
	s_axi3_wstrb	: in std_logic_vector(7 downto 0)	:= (others => '0');
	s_axi3_wlast	: in std_ulogic				:= '0';
	s_axi3_wvalid	: in std_ulogic				:= '0';
	s_axi3_wready	: out std_ulogic			:= '0';
	s_axi3_wcount	: out std_logic_vector(7 downto 0);
	--	write response
	s_axi3_bid	: out std_logic_vector(5 downto 0);
	s_axi3_bresp	: out std_logic_vector(1 downto 0);
	s_axi3_bvalid	: out std_ulogic;
	s_axi3_bready	: in std_ulogic				:= '0'
    );
end entity ps7_stub;

architecture RTL of ps7_stub is
begin
    PS7_inst : PS7
    port map (
	DMA0DATYPE			=> open,		-- out std_logic_vector(1 downto 0);
	DMA0DAVALID			=> open,		-- out std_ulogic;
	DMA0DRREADY			=> open,		-- out std_ulogic;
	DMA0RSTN			=> open,		-- out std_ulogic;
	DMA1DATYPE			=> open,		-- out std_logic_vector(1 downto 0);
	DMA1DAVALID			=> open,		-- out std_ulogic;
	DMA1DRREADY			=> open,		-- out std_ulogic;
	DMA1RSTN			=> open,		-- out std_ulogic;
	DMA2DATYPE			=> open,		-- out std_logic_vector(1 downto 0);
	DMA2DAVALID			=> open,		-- out std_ulogic;
	DMA2DRREADY			=> open,		-- out std_ulogic;
	DMA2RSTN			=> open,		-- out std_ulogic;
	DMA3DATYPE			=> open,		-- out std_logic_vector(1 downto 0);
	DMA3DAVALID			=> open,		-- out std_ulogic;
	DMA3DRREADY			=> open,		-- out std_ulogic;
	DMA3RSTN			=> open,		-- out std_ulogic;
	EMIOCAN0PHYTX			=> open,		-- out std_ulogic;
	EMIOCAN1PHYTX			=> open,		-- out std_ulogic;
	EMIOENET0GMIITXD		=> open,		-- out std_logic_vector(7 downto 0);
	EMIOENET0GMIITXEN		=> open,		-- out std_ulogic;
	EMIOENET0GMIITXER		=> open,		-- out std_ulogic;
	EMIOENET0MDIOMDC		=> open,		-- out std_ulogic;
	EMIOENET0MDIOO			=> open,		-- out std_ulogic;
	EMIOENET0MDIOTN			=> open,		-- out std_ulogic;
	EMIOENET0PTPDELAYREQRX		=> open,		-- out std_ulogic;
	EMIOENET0PTPDELAYREQTX		=> open,		-- out std_ulogic;
	EMIOENET0PTPPDELAYREQRX		=> open,		-- out std_ulogic;
	EMIOENET0PTPPDELAYREQTX		=> open,		-- out std_ulogic;
	EMIOENET0PTPPDELAYRESPRX	=> open,		-- out std_ulogic;
	EMIOENET0PTPPDELAYRESPTX	=> open,		-- out std_ulogic;
	EMIOENET0PTPSYNCFRAMERX		=> open,		-- out std_ulogic;
	EMIOENET0PTPSYNCFRAMETX		=> open,		-- out std_ulogic;
	EMIOENET0SOFRX			=> open,		-- out std_ulogic;
	EMIOENET0SOFTX			=> open,		-- out std_ulogic;
	EMIOENET1GMIITXD		=> open,		-- out std_logic_vector(7 downto 0);
	EMIOENET1GMIITXEN		=> open,		-- out std_ulogic;
	EMIOENET1GMIITXER		=> open,		-- out std_ulogic;
	EMIOENET1MDIOMDC		=> open,		-- out std_ulogic;
	EMIOENET1MDIOO			=> open,		-- out std_ulogic;
	EMIOENET1MDIOTN			=> open,		-- out std_ulogic;
	EMIOENET1PTPDELAYREQRX		=> open,		-- out std_ulogic;
	EMIOENET1PTPDELAYREQTX		=> open,		-- out std_ulogic;
	EMIOENET1PTPPDELAYREQRX		=> open,		-- out std_ulogic;
	EMIOENET1PTPPDELAYREQTX		=> open,		-- out std_ulogic;
	EMIOENET1PTPPDELAYRESPRX	=> open,		-- out std_ulogic;
	EMIOENET1PTPPDELAYRESPTX	=> open,		-- out std_ulogic;
	EMIOENET1PTPSYNCFRAMERX		=> open,		-- out std_ulogic;
	EMIOENET1PTPSYNCFRAMETX		=> open,		-- out std_ulogic;
	EMIOENET1SOFRX			=> open,		-- out std_ulogic;
	EMIOENET1SOFTX			=> open,		-- out std_ulogic;
	EMIOGPIOO			=> emio_gpio_o,		-- out std_logic_vector(63 downto 0);
	EMIOGPIOTN			=> emio_gpio_t_n,	-- out std_logic_vector(63 downto 0);
	EMIOI2C0SCLO			=> i2c0_scl_o,		-- out std_ulogic;
	EMIOI2C0SCLTN			=> i2c0_scl_t_n,	-- out std_ulogic;
	EMIOI2C0SDAO			=> i2c0_sda_o,		-- out std_ulogic;
	EMIOI2C0SDATN			=> i2c0_sda_t_n,	-- out std_ulogic;
	EMIOI2C1SCLO			=> i2c1_scl_o,		-- out std_ulogic;
	EMIOI2C1SCLTN			=> i2c1_scl_t_n,	-- out std_ulogic;
	EMIOI2C1SDAO			=> i2c1_sda_o,		-- out std_ulogic;
	EMIOI2C1SDATN			=> i2c1_sda_t_n,	-- out std_ulogic;
	EMIOPJTAGTDO			=> open,		-- out std_ulogic;
	EMIOPJTAGTDTN			=> open,		-- out std_ulogic;
	EMIOSDIO0BUSPOW			=> open,		-- out std_ulogic;
	EMIOSDIO0BUSVOLT		=> open,		-- out std_logic_vector(2 downto 0);
	EMIOSDIO0CLK			=> open,		-- out std_ulogic;
	EMIOSDIO0CMDO			=> open,		-- out std_ulogic;
	EMIOSDIO0CMDTN			=> open,		-- out std_ulogic;
	EMIOSDIO0DATAO			=> open,		-- out std_logic_vector(3 downto 0);
	EMIOSDIO0DATATN			=> open,		-- out std_logic_vector(3 downto 0);
	EMIOSDIO0LED			=> open,		-- out std_ulogic;
	EMIOSDIO1BUSPOW			=> open,		-- out std_ulogic;
	EMIOSDIO1BUSVOLT		=> open,		-- out std_logic_vector(2 downto 0);
	EMIOSDIO1CLK			=> open,		-- out std_ulogic;
	EMIOSDIO1CMDO			=> open,		-- out std_ulogic;
	EMIOSDIO1CMDTN			=> open,		-- out std_ulogic;
	EMIOSDIO1DATAO			=> open,		-- out std_logic_vector(3 downto 0);
	EMIOSDIO1DATATN			=> open,		-- out std_logic_vector(3 downto 0);
	EMIOSDIO1LED			=> open,		-- out std_ulogic;
	EMIOSPI0MO			=> open,		-- out std_ulogic;
	EMIOSPI0MOTN			=> open,		-- out std_ulogic;
	EMIOSPI0SCLKO			=> open,		-- out std_ulogic;
	EMIOSPI0SCLKTN			=> open,		-- out std_ulogic;
	EMIOSPI0SO			=> open,		-- out std_ulogic;
	EMIOSPI0SSNTN			=> open,		-- out std_ulogic;
	EMIOSPI0SSON			=> open,		-- out std_logic_vector(2 downto 0);
	EMIOSPI0STN			=> open,		-- out std_ulogic;
	EMIOSPI1MO			=> open,		-- out std_ulogic;
	EMIOSPI1MOTN			=> open,		-- out std_ulogic;
	EMIOSPI1SCLKO			=> open,		-- out std_ulogic;
	EMIOSPI1SCLKTN			=> open,		-- out std_ulogic;
	EMIOSPI1SO			=> open,		-- out std_ulogic;
	EMIOSPI1SSNTN			=> open,		-- out std_ulogic;
	EMIOSPI1SSON			=> open,		-- out std_logic_vector(2 downto 0);
	EMIOSPI1STN			=> open,		-- out std_ulogic;
	EMIOTRACECTL			=> open,		-- out std_ulogic;
	EMIOTRACEDATA			=> open,		-- out std_logic_vector(31 downto 0);
	EMIOTTC0WAVEO			=> open,		-- out std_logic_vector(2 downto 0);
	EMIOTTC1WAVEO			=> open,		-- out std_logic_vector(2 downto 0);
	EMIOUART0DTRN			=> open,		-- out std_ulogic;
	EMIOUART0RTSN			=> open,		-- out std_ulogic;
	EMIOUART0TX			=> open,		-- out std_ulogic;
	EMIOUART1DTRN			=> open,		-- out std_ulogic;
	EMIOUART1RTSN			=> open,		-- out std_ulogic;
	EMIOUART1TX			=> open,		-- out std_ulogic;
	EMIOUSB0PORTINDCTL		=> open,		-- out std_logic_vector(1 downto 0);
	EMIOUSB0VBUSPWRSELECT		=> open,		-- out std_ulogic;
	EMIOUSB1PORTINDCTL		=> open,		-- out std_logic_vector(1 downto 0);
	EMIOUSB1VBUSPWRSELECT		=> open,		-- out std_ulogic;
	EMIOWDTRSTO			=> open,		-- out std_ulogic;
	EVENTEVENTO			=> open,		-- out std_ulogic;
	EVENTSTANDBYWFE			=> open,		-- out std_logic_vector(1 downto 0);
	EVENTSTANDBYWFI			=> open,		-- out std_logic_vector(1 downto 0);
	FCLKCLK				=> ps_fclk,		-- out std_logic_vector(3 downto 0);
	FCLKRESETN			=> open,		-- out std_logic_vector(3 downto 0);
	FTMTF2PTRIGACK			=> open,		-- out std_logic_vector(3 downto 0);
	FTMTP2FDEBUG			=> open,		-- out std_logic_vector(31 downto 0);
	FTMTP2FTRIG			=> open,		-- out std_logic_vector(3 downto 0);
	IRQP2F				=> open,		-- out std_logic_vector(28 downto 0);
	MAXIGP0ARADDR			=> m_axi0_araddr,	-- out std_logic_vector(31 downto 0);
	MAXIGP0ARBURST			=> m_axi0_arburst,	-- out std_logic_vector(1 downto 0);
	MAXIGP0ARCACHE			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP0ARESETN			=> m_axi0_areset_n,	-- out std_ulogic;
	MAXIGP0ARID			=> m_axi0_arid,		-- out std_logic_vector(11 downto 0);
	MAXIGP0ARLEN			=> m_axi0_arlen,	-- out std_logic_vector(3 downto 0);
	MAXIGP0ARLOCK			=> open,		-- out std_logic_vector(1 downto 0);
	MAXIGP0ARPROT			=> open,		-- out std_logic_vector(2 downto 0);
	MAXIGP0ARQOS			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP0ARSIZE			=> m_axi0_arsize,	-- out std_logic_vector(1 downto 0);
	MAXIGP0ARVALID			=> m_axi0_arvalid,	-- out std_ulogic;
	MAXIGP0AWADDR			=> m_axi0_awaddr,	-- out std_logic_vector(31 downto 0);
	MAXIGP0AWBURST			=> m_axi0_awburst,	-- out std_logic_vector(1 downto 0);
	MAXIGP0AWCACHE			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP0AWID			=> m_axi0_awid,		-- out std_logic_vector(11 downto 0);
	MAXIGP0AWLEN			=> m_axi0_awlen,	-- out std_logic_vector(3 downto 0);
	MAXIGP0AWLOCK			=> open,		-- out std_logic_vector(1 downto 0);
	MAXIGP0AWPROT			=> open,		-- out std_logic_vector(2 downto 0);
	MAXIGP0AWQOS			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP0AWSIZE			=> m_axi0_awsize,	-- out std_logic_vector(1 downto 0);
	MAXIGP0AWVALID			=> m_axi0_awvalid,	-- out std_ulogic;
	MAXIGP0BREADY			=> m_axi0_bready,	-- out std_ulogic;
	MAXIGP0RREADY			=> m_axi0_rready,	-- out std_ulogic;
	MAXIGP0WDATA			=> m_axi0_wdata,	-- out std_logic_vector(31 downto 0);
	MAXIGP0WID			=> m_axi0_wid,		-- out std_logic_vector(11 downto 0);
	MAXIGP0WLAST			=> m_axi0_wlast,	-- out std_ulogic;
	MAXIGP0WSTRB			=> m_axi0_wstrb,	-- out std_logic_vector(3 downto 0);
	MAXIGP0WVALID			=> m_axi0_wvalid,	-- out std_ulogic;
	MAXIGP1ARADDR			=> m_axi1_araddr,	-- out std_logic_vector(31 downto 0);
	MAXIGP1ARBURST			=> m_axi1_arburst,	-- out std_logic_vector(1 downto 0);
	MAXIGP1ARCACHE			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP1ARESETN			=> m_axi1_areset_n,	-- out std_ulogic;
	MAXIGP1ARID			=> m_axi1_arid,		-- out std_logic_vector(11 downto 0);
	MAXIGP1ARLEN			=> m_axi1_arlen,	-- out std_logic_vector(3 downto 0);
	MAXIGP1ARLOCK			=> open,		-- out std_logic_vector(1 downto 0);
	MAXIGP1ARPROT			=> open,		-- out std_logic_vector(2 downto 0);
	MAXIGP1ARQOS			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP1ARSIZE			=> m_axi1_arsize,	-- out std_logic_vector(1 downto 0);
	MAXIGP1ARVALID			=> m_axi1_arvalid,	-- out std_ulogic;
	MAXIGP1AWADDR			=> m_axi1_awaddr,	-- out std_logic_vector(31 downto 0);
	MAXIGP1AWBURST			=> m_axi1_awburst,	-- out std_logic_vector(1 downto 0);
	MAXIGP1AWCACHE			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP1AWID			=> m_axi1_awid,		-- out std_logic_vector(11 downto 0);
	MAXIGP1AWLEN			=> m_axi1_awlen,	-- out std_logic_vector(3 downto 0);
	MAXIGP1AWLOCK			=> open,		-- out std_logic_vector(1 downto 0);
	MAXIGP1AWPROT			=> open,		-- out std_logic_vector(2 downto 0);
	MAXIGP1AWQOS			=> open,		-- out std_logic_vector(3 downto 0);
	MAXIGP1AWSIZE			=> m_axi1_awsize,	-- out std_logic_vector(1 downto 0);
	MAXIGP1AWVALID			=> m_axi1_awvalid,	-- out std_ulogic;
	MAXIGP1BREADY			=> m_axi1_bready,	-- out std_ulogic;
	MAXIGP1RREADY			=> m_axi1_rready,	-- out std_ulogic;
	MAXIGP1WDATA			=> m_axi1_wdata,	-- out std_logic_vector(31 downto 0);
	MAXIGP1WID			=> m_axi1_wid,		-- out std_logic_vector(11 downto 0);
	MAXIGP1WLAST			=> m_axi1_wlast,	-- out std_ulogic;
	MAXIGP1WSTRB			=> m_axi1_wstrb,	-- out std_logic_vector(3 downto 0);
	MAXIGP1WVALID			=> m_axi1_wvalid,	-- out std_ulogic;
	SAXIACPARESETN			=> open,		-- out std_ulogic;
	SAXIACPARREADY			=> open,		-- out std_ulogic;
	SAXIACPAWREADY			=> open,		-- out std_ulogic;
	SAXIACPBID			=> open,		-- out std_logic_vector(2 downto 0);
	SAXIACPBRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIACPBVALID			=> open,		-- out std_ulogic;
	SAXIACPRDATA			=> open,		-- out std_logic_vector(63 downto 0);
	SAXIACPRID			=> open,		-- out std_logic_vector(2 downto 0);
	SAXIACPRLAST			=> open,		-- out std_ulogic;
	SAXIACPRRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIACPRVALID			=> open,		-- out std_ulogic;
	SAXIACPWREADY			=> open,		-- out std_ulogic;
	SAXIGP0ARESETN			=> open,		-- out std_ulogic;
	SAXIGP0ARREADY			=> open,		-- out std_ulogic;
	SAXIGP0AWREADY			=> open,		-- out std_ulogic;
	SAXIGP0BID			=> open,		-- out std_logic_vector(5 downto 0);
	SAXIGP0BRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIGP0BVALID			=> open,		-- out std_ulogic;
	SAXIGP0RDATA			=> open,		-- out std_logic_vector(31 downto 0);
	SAXIGP0RID			=> open,		-- out std_logic_vector(5 downto 0);
	SAXIGP0RLAST			=> open,		-- out std_ulogic;
	SAXIGP0RRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIGP0RVALID			=> open,		-- out std_ulogic;
	SAXIGP0WREADY			=> open,		-- out std_ulogic;
	SAXIGP1ARESETN			=> open,		-- out std_ulogic;
	SAXIGP1ARREADY			=> open,		-- out std_ulogic;
	SAXIGP1AWREADY			=> open,		-- out std_ulogic;
	SAXIGP1BID			=> open,		-- out std_logic_vector(5 downto 0);
	SAXIGP1BRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIGP1BVALID			=> open,		-- out std_ulogic;
	SAXIGP1RDATA			=> open,		-- out std_logic_vector(31 downto 0);
	SAXIGP1RID			=> open,		-- out std_logic_vector(5 downto 0);
	SAXIGP1RLAST			=> open,		-- out std_ulogic;
	SAXIGP1RRESP			=> open,		-- out std_logic_vector(1 downto 0);
	SAXIGP1RVALID			=> open,		-- out std_ulogic;
	SAXIGP1WREADY			=> open,		-- out std_ulogic;
	SAXIHP0ARESETN			=> s_axi0_areset_n,	-- out std_ulogic;
	SAXIHP0ARREADY			=> s_axi0_arready,	-- out std_ulogic;
	SAXIHP0AWREADY			=> s_axi0_awready,	-- out std_ulogic;
	SAXIHP0BID			=> s_axi0_bid,		-- out std_logic_vector(5 downto 0);
	SAXIHP0BRESP			=> s_axi0_bresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP0BVALID			=> s_axi0_bvalid,	-- out std_ulogic;
	SAXIHP0RACOUNT			=> s_axi0_racount,	-- out std_logic_vector(2 downto 0);
	SAXIHP0RCOUNT			=> s_axi0_rcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP0RDATA			=> s_axi0_rdata,	-- out std_logic_vector(63 downto 0);
	SAXIHP0RID			=> s_axi0_rid,		-- out std_logic_vector(5 downto 0);
	SAXIHP0RLAST			=> s_axi0_rlast,	-- out std_ulogic;
	SAXIHP0RRESP			=> s_axi0_rresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP0RVALID			=> s_axi0_rvalid,	-- out std_ulogic;
	SAXIHP0WACOUNT			=> s_axi0_wacount,	-- out std_logic_vector(5 downto 0);
	SAXIHP0WCOUNT			=> s_axi0_wcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP0WREADY			=> s_axi0_wready,	-- out std_ulogic;
	SAXIHP1ARESETN			=> s_axi1_areset_n,	-- out std_ulogic;
	SAXIHP1ARREADY			=> s_axi1_arready,	-- out std_ulogic;
	SAXIHP1AWREADY			=> s_axi1_awready,	-- out std_ulogic;
	SAXIHP1BID			=> s_axi1_bid,		-- out std_logic_vector(5 downto 0);
	SAXIHP1BRESP			=> s_axi1_bresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP1BVALID			=> s_axi1_bvalid,	-- out std_ulogic;
	SAXIHP1RACOUNT			=> s_axi1_racount,	-- out std_logic_vector(2 downto 0);
	SAXIHP1RCOUNT			=> s_axi1_rcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP1RDATA			=> s_axi1_rdata,	-- out std_logic_vector(63 downto 0);
	SAXIHP1RID			=> s_axi1_rid,		-- out std_logic_vector(5 downto 0);
	SAXIHP1RLAST			=> s_axi1_rlast,	-- out std_ulogic;
	SAXIHP1RRESP			=> s_axi1_rresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP1RVALID			=> s_axi1_rvalid,	-- out std_ulogic;
	SAXIHP1WACOUNT			=> s_axi1_wacount,	-- out std_logic_vector(5 downto 0);
	SAXIHP1WCOUNT			=> s_axi1_wcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP1WREADY			=> s_axi1_wready,	-- out std_ulogic;
	SAXIHP2ARESETN			=> s_axi2_areset_n,	-- out std_ulogic;
	SAXIHP2ARREADY			=> s_axi2_arready,	-- out std_ulogic;
	SAXIHP2AWREADY			=> s_axi2_awready,	-- out std_ulogic;
	SAXIHP2BID			=> s_axi2_bid,		-- out std_logic_vector(5 downto 0);
	SAXIHP2BRESP			=> s_axi2_bresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP2BVALID			=> s_axi2_bvalid,	-- out std_ulogic;
	SAXIHP2RACOUNT			=> s_axi2_racount,	-- out std_logic_vector(2 downto 0);
	SAXIHP2RCOUNT			=> s_axi2_rcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP2RDATA			=> s_axi2_rdata,	-- out std_logic_vector(63 downto 0);
	SAXIHP2RID			=> s_axi2_rid,		-- out std_logic_vector(5 downto 0);
	SAXIHP2RLAST			=> s_axi2_rlast,	-- out std_ulogic;
	SAXIHP2RRESP			=> s_axi2_rresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP2RVALID			=> s_axi2_rvalid,	-- out std_ulogic;
	SAXIHP2WACOUNT			=> s_axi2_wacount,	-- out std_logic_vector(5 downto 0);
	SAXIHP2WCOUNT			=> s_axi2_wcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP2WREADY			=> s_axi2_wready,	-- out std_ulogic;
	SAXIHP3ARESETN			=> s_axi3_areset_n,	-- out std_ulogic;
	SAXIHP3ARREADY			=> s_axi3_arready,	-- out std_ulogic;
	SAXIHP3AWREADY			=> s_axi3_awready,	-- out std_ulogic;
	SAXIHP3BID			=> s_axi3_bid,		-- out std_logic_vector(5 downto 0);
	SAXIHP3BRESP			=> s_axi3_bresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP3BVALID			=> s_axi3_bvalid,	-- out std_ulogic;
	SAXIHP3RACOUNT			=> s_axi3_racount,	-- out std_logic_vector(2 downto 0);
	SAXIHP3RCOUNT			=> s_axi3_rcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP3RDATA			=> s_axi3_rdata,	-- out std_logic_vector(63 downto 0);
	SAXIHP3RID			=> s_axi3_rid,		-- out std_logic_vector(5 downto 0);
	SAXIHP3RLAST			=> s_axi3_rlast,	-- out std_ulogic;
	SAXIHP3RRESP			=> s_axi3_rresp,	-- out std_logic_vector(1 downto 0);
	SAXIHP3RVALID			=> s_axi3_rvalid,	-- out std_ulogic;
	SAXIHP3WACOUNT			=> s_axi3_wacount,	-- out std_logic_vector(5 downto 0);
	SAXIHP3WCOUNT			=> s_axi3_wcount,	-- out std_logic_vector(7 downto 0);
	SAXIHP3WREADY			=> s_axi3_wready,	-- out std_ulogic;
	DDRA				=> ddr_addr,		-- inout std_logic_vector(14 downto 0);
	DDRBA				=> ddr_bankaddr,	-- inout std_logic_vector(2 downto 0);
	DDRCASB				=> ddr_cas_n,		-- inout std_ulogic;
	DDRCKE				=> ddr_cke,		-- inout std_ulogic;
	DDRCKN				=> ddr_clk_n,		-- inout std_ulogic;
	DDRCKP				=> ddr_clk,		-- inout std_ulogic;
	DDRCSB				=> ddr_cs_n,		-- inout std_ulogic;
	DDRDM				=> ddr_dm,		-- inout std_logic_vector(3 downto 0);
	DDRDQ				=> ddr_dq,		-- inout std_logic_vector(31 downto 0);
	DDRDQSN				=> ddr_dqs_n,		-- inout std_logic_vector(3 downto 0);
	DDRDQSP				=> ddr_dqs,		-- inout std_logic_vector(3 downto 0);
	DDRDRSTB			=> ddr_drstb,		-- inout std_ulogic;
	DDRODT				=> ddr_odt,		-- inout std_ulogic;
	DDRRASB				=> ddr_ras_n,		-- inout std_ulogic;
	DDRVRN				=> ddr_vr_n,		-- inout std_ulogic;
	DDRVRP				=> ddr_vr,		-- inout std_ulogic;
	DDRWEB				=> ddr_web,		-- inout std_ulogic;
	MIO				=> ps_mio,		-- inout std_logic_vector(53 downto 0);
	PSCLK				=> ps_clk,		-- inout std_ulogic;
	PSPORB				=> ps_porb,		-- inout std_ulogic;
	PSSRSTB				=> ps_srstb,		-- inout std_ulogic;
	DDRARB				=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	DMA0ACLK			=> '0',			-- in std_ulogic;
	DMA0DAREADY			=> '0',			-- in std_ulogic;
	DMA0DRLAST			=> '0',			-- in std_ulogic;
	DMA0DRTYPE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	DMA0DRVALID			=> '0',			-- in std_ulogic;
	DMA1ACLK			=> '0',			-- in std_ulogic;
	DMA1DAREADY			=> '0',			-- in std_ulogic;
	DMA1DRLAST			=> '0',			-- in std_ulogic;
	DMA1DRTYPE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	DMA1DRVALID			=> '0',			-- in std_ulogic;
	DMA2ACLK			=> '0',			-- in std_ulogic;
	DMA2DAREADY			=> '0',			-- in std_ulogic;
	DMA2DRLAST			=> '0',			-- in std_ulogic;
	DMA2DRTYPE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	DMA2DRVALID			=> '0',			-- in std_ulogic;
	DMA3ACLK			=> '0',			-- in std_ulogic;
	DMA3DAREADY			=> '0',			-- in std_ulogic;
	DMA3DRLAST			=> '0',			-- in std_ulogic;
	DMA3DRTYPE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	DMA3DRVALID			=> '0',			-- in std_ulogic;
	EMIOCAN0PHYRX			=> '0',			-- in std_ulogic;
	EMIOCAN1PHYRX			=> '0',			-- in std_ulogic;
	EMIOENET0EXTINTIN		=> '0',			-- in std_ulogic;
	EMIOENET0GMIICOL		=> '0',			-- in std_ulogic;
	EMIOENET0GMIICRS		=> '0',			-- in std_ulogic;
	EMIOENET0GMIIRXCLK		=> '0',			-- in std_ulogic;
	EMIOENET0GMIIRXD		=> (others => '0'),	-- in std_logic_vector(7 downto 0);
	EMIOENET0GMIIRXDV		=> '0',			-- in std_ulogic;
	EMIOENET0GMIIRXER		=> '0',			-- in std_ulogic;
	EMIOENET0GMIITXCLK		=> '0',			-- in std_ulogic;
	EMIOENET0MDIOI			=> '0',			-- in std_ulogic;
	EMIOENET1EXTINTIN		=> '0',			-- in std_ulogic;
	EMIOENET1GMIICOL		=> '0',			-- in std_ulogic;
	EMIOENET1GMIICRS		=> '0',			-- in std_ulogic;
	EMIOENET1GMIIRXCLK		=> '0',			-- in std_ulogic;
	EMIOENET1GMIIRXD		=> (others => '0'),	-- in std_logic_vector(7 downto 0);
	EMIOENET1GMIIRXDV		=> '0',			-- in std_ulogic;
	EMIOENET1GMIIRXER		=> '0',			-- in std_ulogic;
	EMIOENET1GMIITXCLK		=> '0',			-- in std_ulogic;
	EMIOENET1MDIOI			=> '0',			-- in std_ulogic;
	EMIOGPIOI			=> emio_gpio_i,		-- in std_logic_vector(63 downto 0);
	EMIOI2C0SCLI			=> i2c0_scl_i,		-- in std_ulogic;
	EMIOI2C0SDAI			=> i2c0_sda_i,		-- in std_ulogic;
	EMIOI2C1SCLI			=> i2c1_scl_i,		-- in std_ulogic;
	EMIOI2C1SDAI			=> i2c1_sda_i,		-- in std_ulogic;
	EMIOPJTAGTCK			=> '0',			-- in std_ulogic;
	EMIOPJTAGTDI			=> '0',			-- in std_ulogic;
	EMIOPJTAGTMS			=> '0',			-- in std_ulogic;
	EMIOSDIO0CDN			=> '0',			-- in std_ulogic;
	EMIOSDIO0CLKFB			=> '0',			-- in std_ulogic;
	EMIOSDIO0CMDI			=> '0',			-- in std_ulogic;
	EMIOSDIO0DATAI			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	EMIOSDIO0WP			=> '0',			-- in std_ulogic;
	EMIOSDIO1CDN			=> '0',			-- in std_ulogic;
	EMIOSDIO1CLKFB			=> '0',			-- in std_ulogic;
	EMIOSDIO1CMDI			=> '0',			-- in std_ulogic;
	EMIOSDIO1DATAI			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	EMIOSDIO1WP			=> '0',			-- in std_ulogic;
	EMIOSPI0MI			=> '0',			-- in std_ulogic;
	EMIOSPI0SCLKI			=> '0',			-- in std_ulogic;
	EMIOSPI0SI			=> '0',			-- in std_ulogic;
	EMIOSPI0SSIN			=> '0',			-- in std_ulogic;
	EMIOSPI1MI			=> '0',			-- in std_ulogic;
	EMIOSPI1SCLKI			=> '0',			-- in std_ulogic;
	EMIOSPI1SI			=> '0',			-- in std_ulogic;
	EMIOSPI1SSIN			=> '0',			-- in std_ulogic;
	EMIOSRAMINTIN			=> '0',			-- in std_ulogic;
	EMIOTRACECLK			=> '0',			-- in std_ulogic;
	EMIOTTC0CLKI			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	EMIOTTC1CLKI			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	EMIOUART0CTSN			=> '0',			-- in std_ulogic;
	EMIOUART0DCDN			=> '0',			-- in std_ulogic;
	EMIOUART0DSRN			=> '0',			-- in std_ulogic;
	EMIOUART0RIN			=> '0',			-- in std_ulogic;
	EMIOUART0RX			=> '0',			-- in std_ulogic;
	EMIOUART1CTSN			=> '0',			-- in std_ulogic;
	EMIOUART1DCDN			=> '0',			-- in std_ulogic;
	EMIOUART1DSRN			=> '0',			-- in std_ulogic;
	EMIOUART1RIN			=> '0',			-- in std_ulogic;
	EMIOUART1RX			=> '0',			-- in std_ulogic;
	EMIOUSB0VBUSPWRFAULT		=> '0',			-- in std_ulogic;
	EMIOUSB1VBUSPWRFAULT		=> '0',			-- in std_ulogic;
	EMIOWDTCLKI			=> '0',			-- in std_ulogic;
	EVENTEVENTI			=> '0',			-- in std_ulogic;
	FCLKCLKTRIGN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	FPGAIDLEN			=> '0',			-- in std_ulogic;
	FTMDTRACEINATID			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	FTMDTRACEINCLOCK		=> '0',			-- in std_ulogic;
	FTMDTRACEINDATA			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	FTMDTRACEINVALID		=> '0',			-- in std_ulogic;
	FTMTF2PDEBUG			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	FTMTF2PTRIG			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	FTMTP2FTRIGACK			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	IRQF2P				=> (others => '0'),	-- in std_logic_vector(19 downto 0);
	MAXIGP0ACLK			=> m_axi0_aclk,		-- in std_ulogic;
	MAXIGP0ARREADY			=> m_axi0_arready,	-- in std_ulogic;
	MAXIGP0AWREADY			=> m_axi0_awready,	-- in std_ulogic;
	MAXIGP0BID			=> m_axi0_bid,		-- in std_logic_vector(11 downto 0);
	MAXIGP0BRESP			=> m_axi0_bresp,	-- in std_logic_vector(1 downto 0);
	MAXIGP0BVALID			=> m_axi0_bvalid,	-- in std_ulogic;
	MAXIGP0RDATA			=> m_axi0_rdata,	-- in std_logic_vector(31 downto 0);
	MAXIGP0RID			=> m_axi0_rid,		-- in std_logic_vector(11 downto 0);
	MAXIGP0RLAST			=> m_axi0_rlast,	-- in std_ulogic;
	MAXIGP0RRESP			=> m_axi0_rresp,	-- in std_logic_vector(1 downto 0);
	MAXIGP0RVALID			=> m_axi0_rvalid,	-- in std_ulogic;
	MAXIGP0WREADY			=> m_axi0_wready,	-- in std_ulogic;
	MAXIGP1ACLK			=> m_axi1_aclk,		-- in std_ulogic;
	MAXIGP1ARREADY			=> m_axi1_arready,	-- in std_ulogic;
	MAXIGP1AWREADY			=> m_axi1_awready,	-- in std_ulogic;
	MAXIGP1BID			=> m_axi1_bid,		-- in std_logic_vector(11 downto 0);
	MAXIGP1BRESP			=> m_axi1_bresp,	-- in std_logic_vector(1 downto 0);
	MAXIGP1BVALID			=> m_axi1_bvalid,	-- in std_ulogic;
	MAXIGP1RDATA			=> m_axi1_rdata,	-- in std_logic_vector(31 downto 0);
	MAXIGP1RID			=> m_axi1_rid,		-- in std_logic_vector(11 downto 0);
	MAXIGP1RLAST			=> m_axi1_rlast,	-- in std_ulogic;
	MAXIGP1RRESP			=> m_axi1_rresp,	-- in std_logic_vector(1 downto 0);
	MAXIGP1RVALID			=> m_axi1_rvalid,	-- in std_ulogic;
	MAXIGP1WREADY			=> m_axi1_wready,	-- in std_ulogic;
	SAXIACPACLK			=> '0',			-- in std_ulogic;
	SAXIACPARADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIACPARBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPARCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPARID			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIACPARLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIACPARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPARSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPARUSER			=> (others => '0'),	-- in std_logic_vector(4 downto 0);
	SAXIACPARVALID			=> '0',			-- in std_ulogic;
	SAXIACPAWADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIACPAWBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPAWCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPAWID			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIACPAWLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPAWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPAWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIACPAWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIACPAWSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIACPAWUSER			=> (others => '0'),	-- in std_logic_vector(4 downto 0);
	SAXIACPAWVALID			=> '0',			-- in std_ulogic;
	SAXIACPBREADY			=> '0',			-- in std_ulogic;
	SAXIACPRREADY			=> '0',			-- in std_ulogic;
	SAXIACPWDATA			=> (others => '0'),	-- in std_logic_vector(63 downto 0);
	SAXIACPWID			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIACPWLAST			=> '0',			-- in std_ulogic;
	SAXIACPWSTRB			=> (others => '0'),	-- in std_logic_vector(7 downto 0);
	SAXIACPWVALID			=> '0',			-- in std_ulogic;
	SAXIGP0ACLK			=> '0',			-- in std_ulogic;
	SAXIGP0ARADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP0ARBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0ARCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0ARID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP0ARLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIGP0ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0ARSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0ARVALID			=> '0',			-- in std_ulogic;
	SAXIGP0AWADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP0AWBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0AWCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0AWID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP0AWLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIGP0AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0AWSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP0AWVALID			=> '0',			-- in std_ulogic;
	SAXIGP0BREADY			=> '0',			-- in std_ulogic;
	SAXIGP0RREADY			=> '0',			-- in std_ulogic;
	SAXIGP0WDATA			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP0WID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP0WLAST			=> '0',			-- in std_ulogic;
	SAXIGP0WSTRB			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP0WVALID			=> '0',			-- in std_ulogic;
	SAXIGP1ACLK			=> '0',			-- in std_ulogic;
	SAXIGP1ARADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP1ARBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1ARCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1ARID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP1ARLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIGP1ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1ARSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1ARVALID			=> '0',			-- in std_ulogic;
	SAXIGP1AWADDR			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP1AWBURST			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1AWCACHE			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1AWID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP1AWLEN			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIGP1AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1AWSIZE			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIGP1AWVALID			=> '0',			-- in std_ulogic;
	SAXIGP1BREADY			=> '0',			-- in std_ulogic;
	SAXIGP1RREADY			=> '0',			-- in std_ulogic;
	SAXIGP1WDATA			=> (others => '0'),	-- in std_logic_vector(31 downto 0);
	SAXIGP1WID			=> (others => '0'),	-- in std_logic_vector(5 downto 0);
	SAXIGP1WLAST			=> '0',			-- in std_ulogic;
	SAXIGP1WSTRB			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIGP1WVALID			=> '0',			-- in std_ulogic;
	SAXIHP0ACLK			=> s_axi0_aclk,		-- in std_ulogic;
	SAXIHP0ARADDR			=> s_axi0_araddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP0ARBURST			=> s_axi0_arburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP0ARCACHE			=> s_axi0_arcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP0ARID			=> s_axi0_arid,		-- in std_logic_vector(5 downto 0);
	SAXIHP0ARLEN			=> s_axi0_arlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP0ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP0ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP0ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP0ARSIZE			=> s_axi0_arsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP0ARVALID			=> s_axi0_arvalid,	-- in std_ulogic;
	SAXIHP0AWADDR			=> s_axi0_awaddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP0AWBURST			=> s_axi0_awburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP0AWCACHE			=> s_axi0_awcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP0AWID			=> s_axi0_awid,		-- in std_logic_vector(5 downto 0);
	SAXIHP0AWLEN			=> s_axi0_awlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP0AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP0AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP0AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP0AWSIZE			=> s_axi0_awsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP0AWVALID			=> s_axi0_awvalid,	-- in std_ulogic;
	SAXIHP0BREADY			=> s_axi0_bready,	-- in std_ulogic;
	SAXIHP0RDISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP0RREADY			=> s_axi0_rready,	-- in std_ulogic;
	SAXIHP0WDATA			=> s_axi0_wdata,	-- in std_logic_vector(63 downto 0);
	SAXIHP0WID			=> s_axi0_wid,		-- in std_logic_vector(5 downto 0);
	SAXIHP0WLAST			=> s_axi0_wlast,	-- in std_ulogic;
	SAXIHP0WRISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP0WSTRB			=> s_axi0_wstrb,	-- in std_logic_vector(7 downto 0);
	SAXIHP0WVALID			=> s_axi0_wvalid,	-- in std_ulogic;
	SAXIHP1ACLK			=> s_axi1_aclk,		-- in std_ulogic;
	SAXIHP1ARADDR			=> s_axi1_araddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP1ARBURST			=> s_axi1_arburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP1ARCACHE			=> s_axi1_arcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP1ARID			=> s_axi1_arid,		-- in std_logic_vector(5 downto 0);
	SAXIHP1ARLEN			=> s_axi1_arlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP1ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP1ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP1ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP1ARSIZE			=> s_axi1_arsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP1ARVALID			=> s_axi1_arvalid,	-- in std_ulogic;
	SAXIHP1AWADDR			=> s_axi1_awaddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP1AWBURST			=> s_axi1_awburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP1AWCACHE			=> s_axi1_awcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP1AWID			=> s_axi1_awid,		-- in std_logic_vector(5 downto 0);
	SAXIHP1AWLEN			=> s_axi1_awlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP1AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP1AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP1AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP1AWSIZE			=> s_axi1_awsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP1AWVALID			=> s_axi1_awvalid,	-- in std_ulogic;
	SAXIHP1BREADY			=> s_axi1_bready,	-- in std_ulogic;
	SAXIHP1RDISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP1RREADY			=> s_axi1_rready,	-- in std_ulogic;
	SAXIHP1WDATA			=> s_axi1_wdata,	-- in std_logic_vector(63 downto 0);
	SAXIHP1WID			=> s_axi1_wid,		-- in std_logic_vector(5 downto 0);
	SAXIHP1WLAST			=> s_axi1_wlast,	-- in std_ulogic;
	SAXIHP1WRISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP1WSTRB			=> s_axi1_wstrb,	-- in std_logic_vector(7 downto 0);
	SAXIHP1WVALID			=> s_axi1_wvalid,	-- in std_ulogic;
	SAXIHP2ACLK			=> s_axi2_aclk,		-- in std_ulogic;
	SAXIHP2ARADDR			=> s_axi2_araddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP2ARBURST			=> s_axi2_arburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP2ARCACHE			=> s_axi2_arcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP2ARID			=> s_axi2_arid,		-- in std_logic_vector(5 downto 0);
	SAXIHP2ARLEN			=> s_axi2_arlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP2ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP2ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP2ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP2ARSIZE			=> s_axi2_arsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP2ARVALID			=> s_axi2_arvalid,	-- in std_ulogic;
	SAXIHP2AWADDR			=> s_axi2_awaddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP2AWBURST			=> s_axi2_awburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP2AWCACHE			=> s_axi2_awcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP2AWID			=> s_axi2_awid,		-- in std_logic_vector(5 downto 0);
	SAXIHP2AWLEN			=> s_axi2_awlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP2AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP2AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP2AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP2AWSIZE			=> s_axi2_awsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP2AWVALID			=> s_axi2_awvalid,	-- in std_ulogic;
	SAXIHP2BREADY			=> s_axi2_bready,	-- in std_ulogic;
	SAXIHP2RDISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP2RREADY			=> s_axi2_rready,	-- in std_ulogic;
	SAXIHP2WDATA			=> s_axi2_wdata,	-- in std_logic_vector(63 downto 0);
	SAXIHP2WID			=> s_axi2_wid,		-- in std_logic_vector(5 downto 0);
	SAXIHP2WLAST			=> s_axi2_wlast,	-- in std_ulogic;
	SAXIHP2WRISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP2WSTRB			=> s_axi2_wstrb,	-- in std_logic_vector(7 downto 0);
	SAXIHP2WVALID			=> s_axi2_wvalid,	-- in std_ulogic;
	SAXIHP3ACLK			=> s_axi3_aclk,		-- in std_ulogic;
	SAXIHP3ARADDR			=> s_axi3_araddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP3ARBURST			=> s_axi3_arburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP3ARCACHE			=> s_axi3_arcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP3ARID			=> s_axi3_arid,		-- in std_logic_vector(5 downto 0);
	SAXIHP3ARLEN			=> s_axi3_arlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP3ARLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP3ARPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP3ARQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP3ARSIZE			=> s_axi3_arsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP3ARVALID			=> s_axi3_arvalid,	-- in std_ulogic;
	SAXIHP3AWADDR			=> s_axi3_awaddr,	-- in std_logic_vector(31 downto 0);
	SAXIHP3AWBURST			=> s_axi3_awburst,	-- in std_logic_vector(1 downto 0);
	SAXIHP3AWCACHE			=> s_axi3_awcache,	-- in std_logic_vector(3 downto 0);
	SAXIHP3AWID			=> s_axi3_awid,		-- in std_logic_vector(5 downto 0);
	SAXIHP3AWLEN			=> s_axi3_awlen,	-- in std_logic_vector(3 downto 0);
	SAXIHP3AWLOCK			=> (others => '0'),	-- in std_logic_vector(1 downto 0);
	SAXIHP3AWPROT			=> (others => '0'),	-- in std_logic_vector(2 downto 0);
	SAXIHP3AWQOS			=> (others => '0'),	-- in std_logic_vector(3 downto 0);
	SAXIHP3AWSIZE			=> s_axi3_awsize,	-- in std_logic_vector(1 downto 0);
	SAXIHP3AWVALID			=> s_axi3_awvalid,	-- in std_ulogic;
	SAXIHP3BREADY			=> s_axi3_bready,	-- in std_ulogic;
	SAXIHP3RDISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP3RREADY			=> s_axi3_rready,	-- in std_ulogic;
	SAXIHP3WDATA			=> s_axi3_wdata,	-- in std_logic_vector(63 downto 0);
	SAXIHP3WID			=> s_axi3_wid,		-- in std_logic_vector(5 downto 0);
	SAXIHP3WLAST			=> s_axi3_wlast,	-- in std_ulogic;
	SAXIHP3WRISSUECAP1EN		=> '0',			-- in std_ulogic;
	SAXIHP3WSTRB			=> s_axi3_wstrb,	-- in std_logic_vector(7 downto 0);
	SAXIHP3WVALID			=> s_axi3_wvalid	-- in std_ulogic;
    );
end RTL;