----------------------------------------------------------------------------
--  data_gen.vhd
--	Data Generator
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity data_gen is
    generic (
	DATA_WIDTH : natural := 64 );
    port (
	clk	: in std_logic;			-- base clock
	reset_n	: in std_logic;			-- reset
	enable	: in std_logic;			-- enable
	--
	data_min : in std_logic_vector(DATA_WIDTH - 1 downto 0);
	data_inc : in std_logic_vector(DATA_WIDTH - 1 downto 0);
	data_max : in std_logic_vector(DATA_WIDTH - 1 downto 0);
	--
	data	: out std_logic_vector(DATA_WIDTH - 1 downto 0)
    );

end entity data_gen;

architecture RTL of data_gen is
begin

    data_proc: process(clk)

	variable data_v : unsigned(DATA_WIDTH - 1 downto 0);

    begin
	data <= (others => '0');

	if rising_edge(clk) then

	    if reset_n = '0' then			-- reset
		data_v := unsigned(data_min);

	    elsif enable = '1' then			-- enabled
		if data_v = unsigned(data_max) then
		    data_v := unsigned(data_min);
		else
		    data_v := data_v + unsigned(data_inc);
		end if;
	
	    else
		null;

	    end if;

	data <= std_logic_vector(data_v);

	end if;

    end process;

end RTL;