----------------------------------------------------------------------------
--  axi_mmcm.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.VCOMPONENTS.all;

entity axi_mmcm is
    port (
	clk_in : in std_logic;		-- input clock to FPGA
	reset_n : in std_logic;		-- reset
	--
	mmcm_clk : out std_logic_vector(6 downto 0);
	--
	mmcm_locked : out std_logic	-- MMCM locked
    );

end entity axi_mmcm;


architecture RTL of axi_mmcm is

    signal mmcm_reset : std_logic;

    signal mmcm_fbout : std_logic;
    signal mmcm_fbin : std_logic;

    signal mmcm_clk_out : std_logic_vector(6 downto 0);

begin
    axi_mmcm_inst : MMCME2_BASE
    generic map (
	BANDWIDTH => "OPTIMIZED",
	CLKIN1_PERIOD => 10.0,
	CLKFBOUT_MULT_F => 10.0,
	CLKOUT0_DIVIDE_F => 100.00,	--  10MHz PMOD
	CLKOUT1_DIVIDE => 1000/150,	-- 150MHz AXI HP slave
	CLKOUT2_DIVIDE => 1000/150,	-- 150MHz AXI HP slave
	CLKOUT3_DIVIDE => 1000/150,	-- 150MHz AXI HP slave
	CLKOUT4_DIVIDE => 1000/150,	-- 150MHz AXI HP slave
	CLKOUT5_DIVIDE => 1000/100,	-- 100MHz AXI GP
	CLKOUT6_DIVIDE => 1000/100,	-- 100MHz AXI GP
	DIVCLK_DIVIDE => 1 )
    port map (
	CLKIN1 => clk_in,
	CLKFBOUT => mmcm_fbout,
	CLKFBIN => mmcm_fbin,

	CLKOUT0 => mmcm_clk_out(6),
	CLKOUT1 => mmcm_clk_out(0),
	CLKOUT2 => mmcm_clk_out(1),
	CLKOUT3 => mmcm_clk_out(2),
	CLKOUT4 => mmcm_clk_out(3),
	CLKOUT5 => mmcm_clk_out(4),
	CLKOUT6 => mmcm_clk_out(5),

	LOCKED => mmcm_locked,
	PWRDWN => '0',
	RST => mmcm_reset );

    mmcm_reset <= not reset_n;

    BUFG_inst : BUFG
	port map (
	    I => mmcm_fbout,
	    O => mmcm_fbin );

    GEN_BUF : for N in 0 to 6 generate
	BUFG_inst : BUFG
	    port map (
		I => mmcm_clk_out(N),
		O => mmcm_clk(N) );
    end generate GEN_BUF;

end RTL;